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| www..com MCP4728 12-Bit, Quad Digital-to-Analog Converter with EEPROM Memory Features * 12-Bit Voltage Output DAC with 4 Buffered Outputs * On-Board Non-Volatile Memory (EEPROM) for DAC Codes and I2CTM Address Bits * Internal or External Voltage Reference Selection * Output Voltage Range: - Using Internal VREF (2.048V): 0.000V to 2.048V with Gain Setting = 1 0.000V to 4.096V with Gain Setting = 2 - Using External VREF (VDD): 0.000V to VDD * 0.2 LSB DNL (typical) * Fast Settling Time: 6 s (typical) * Normal or Power-Down Mode * Low Power Consumption * Single-Supply Operation: 2.7V to 5.5V * I2C Interface: - Address bits: User Programmable to EEPROM - Standard (100 kbps), Fast (400 kbps) and High Speed (3.4 Mbps) Modes * 10-Lead MSOP Package * Extended Temperature Range: -40C to +125C Description The MCP4728 device is a quad, 12-bit voltage output Digital-to-Analog Convertor (DAC) with non-volatile memory (EEPROM). Its on-board precision output amplifier allows it to achieve rail-to-rail analog output swing. The DAC input codes, device configuration bits, and I2C address bits are programmable to the non-volatile memory (EEPROM) by using I2C serial interface commands. The non-volatile memory feature enables the DAC device to hold the DAC input codes during power-off time, allowing the DAC outputs to be available immediately after power-up with the saved settings. This feature is very useful when the DAC device is used as a supporting device for other devices in applications network. The MCP4728 device has a high precision internal voltage reference (VREF = 2.048V). The user can select the internal reference or external reference (VDD) for each channel individually. Each channel can be operated in normal mode or power-down mode individually by setting the configuration register bits. In power-down mode, most of the internal circuits in the powered down channel are turned off for power-savings and the output amplifier can be configured to present a known low, medium, or high resistance output load. The MCP4728 device includes a Power-On-Reset (POR) circuit to ensure reliable power-up and an on-board charge pump for the EEPROM programming voltage. The MCP4728 has a two-wire I2C compatible serial interface for standard (100 kHz), fast (400 kHz), or high speed (3.4 MHz) mode. The MCP4728 DAC is an ideal device for applications requiring design simplicity with high precision, and for applications requiring the DAC device settings to be saved during power-off time. The MCP4728 device is available in a 10-lead MSOP package and operates from a single 2.7V to 5.5V supply voltage. Applications * * * * * * * * Set Point or Offset Adjustment Sensor Calibration Closed-Loop Servo Control Low Power Portable Instrumentation PC Peripherals Programmable Voltage and Current Source Industrial Process Control Instrumentation (c) 2009 Microchip Technology Inc. DS22187A-page 1 MCP4728 www..com Package Type MSOP-10 VDD 1 SCL 2 SDA 3 LDAC 4 RDY/BSY 5 MCP4728 10 VSS 9 VOUT D 8 VOUT C 7 VOUT B 6 VOUT A Functional Block Diagram LDAC EEPROM A VREF A Output Logic OP AMP A Power Down Control VDD VSS INPUT REGISTER A EEPROM B UDAC Gain Control OUTPUT REGISTER A UDAC STRING DAC A VOUT A VREF B Gain Control Output Logic I2C Interface Logic INPUT REGISTER B EEPROM C OUTPUT REGISTER B UDAC STRING DAC B OP AMP B Power Down Control OP AMP C Power Down Control OP AMP D Power Down Control Output Logic VOUT B SDA SCL VREF C Gain Control Output Logic INPUT REGISTER C EEPROM D OUTPUT REGISTER C UDAC STRING DAC C VREF D Gain Control VOUT C RDY/BSY INPUT REGISTER D Internal VREF (2.048V) VDD OUTPUT REGISTER D VREF Selector STRING DAC D VREF VOUT D (VREF A, VREF B, VREF C, VREF D) DS22187A-page 2 (c) 2009 Microchip Technology Inc. MCP4728 www..com 1.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings VDD...................................................................................6.5V All inputs and outputs w.r.t VSS .................-0.3V to VDD+0.3V Current at Input Pins ....................................................2 mA Current at Supply Pins ............................................. 110 mA Current at Output Pins ...............................................25 mA Storage Temperature ...................................-65C to +150C Ambient Temp. with Power Applied .............-55C to +125C ESD protection on all pins ................ 4 kV HBM, 400V MM Maximum Junction Temperature (TJ) ......................... +150C Notice: Stresses above those listed under "Maximum ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability TABLE 1-1: ELECTRICAL CHARACTERISTICS Electrical Specifications: Unless otherwise indicated, all parameters apply at VDD = + 2.7V to 5.5V, VSS = 0V, RL = 5 k, CL = 100 pF, GX = 1, TA = -40C to +125C. Typical values are at +25C, VIH = VDD, VIL = VSS. Parameter Power Requirements Operating Voltage Supply Current with External Reference (VREF = VDD ) (Note 1) VDD IDD_EXT 2.7 -- -- -- -- Power-Down Current withExternal Reference Supply Current with Internal Reference (VREF = Internal) (Note 1) IPD_EXT IDD_INT -- -- 800 600 400 200 40 800 5.5 1400 -- -- -- -- 1400 V A A A A nA A VREF = VDD, VDD = 5.5V All 4 channels are in normal mode. 3 channels are in normal mode, 1 channel is powered down. 2 channels are in normal mode, 2 channel are powered down. 1 channel is in normal mode, 3 channels are powered down. All 4 channels are powered down. (VREF = VDD) VREF = Internal Reference VDD = 5.5V All 4 channels are in normal mode. 3 channels are in normal mode, 1 channel is powered down. 2 channels are in normal mode, 2 channels are powered down. 1 channel is in normal mode, 3 channels are powered down. All 4 channels are powered down. VREF = Internal Reference Symbol Min Typical Max Units Conditions -- -- -- 600 400 200 45 -- -- -- 60 A A A A Power-Down Current with Internal Reference Note 1: 2: 3: 4: 5: 6: 7: 8: 9: IPD_INT -- All digital input pins (SDA, SCL, LDAC) are tied to "High", Output pins are unloaded, code = 0x000. The power-up ramp rate measures the rise of VDD over time. This parameter is ensured by design and not 100% tested. This parameter is ensured by characterization and not 100% tested. Test code range: 100 - 4000 codes, VREF = VDD, VDD = 5.5V. Time delay to settle to a new reference when switching from external to internal reference or vice versa. This parameter is indirectly tested by Offset and Gain error testing. Within 1/2 LSB of the final value when code changes from 1/4 of to 3/4 of full scale. This time delay is measured from the falling edge of ACK pulse in I2C command to the beginning of VOUT. This time delay is not included in the output settling time specification. (c) 2009 Microchip Technology Inc. DS22187A-page 3 MCP4728 www..com TABLE 1-1: ELECTRICAL CHARACTERISTICS (CONTINUED) Electrical Specifications: Unless otherwise indicated, all parameters apply at VDD = + 2.7V to 5.5V, VSS = 0V, RL = 5 k, CL = 100 pF, GX = 1, TA = -40C to +125C. Typical values are at +25C, VIH = VDD, VIL = VSS. Parameter Power-On-Reset Threshold Voltage Power-Up Ramp Rate DC Accuracy Resolution INL Error DNL Error Offset Error Offset Error Drift Gain Error n INL DNL VOS VOS/C GE 12 -- -0.75 -- -- -- -3 -- 2 0.2 0.02 0.16 0.44 -0.1 -- 13 0.75 0.75 -- -- 3 Bits LSB LSB % of FSR Code Change: 000h to FFFh (Note 5) (Note 5) Code = 000h Symbol VPOR VRAMP Min -- 1 Typical 2.2 -- Max -- -- Units V V/s Conditions All circuits including EEPROM are ready to operate. Note 2, Note 4 ppm/C -45C to 25C ppm/C +25C to +125C % of FSR % of FSR % of FSR ppm/C V ppm/C -40 to 0C LSB/C -40 to 0C ppm/C 0 to +125C LSB/C 0 to +125C Vp-p V HZ Hz V (Note 7) Code = FFFh, 0.1 - 10 Hz, Gx=1 Code = FFFh, 1 kHz, Gx=1 Code = FFFh, 10 kHz, Gx=1 VREF = Internal, Gain = x1 Code = FFFh, Offset error is not included. VREF = Internal, Gain = x2 Code = FFFh, Offset error is not included. VREF = VDD Code = FFFh, Offset error is not included. -3 -0.1 3 -2 -0.1 2 Gain Error Drift Internal Voltage Reference Temperature Coefficient GE/C VREF VREF/C -- 2.007 -- -- -- -- -3 2.048 125 0.25 45 0.09 290 1.2 1.0 400 FSR -- 2.089 -- -- -- -- -- -- -- -- -- Internal Voltage Reference (VREF), (Note 3) Reference Output Noise Output Noise Density 1/f Corner Frequency Output Voltage Swing Note 1: 2: 3: 4: 5: 6: 7: 8: 9: ENREF eNREF fCORNER VOUT -- -- -- -- -- Analog Output (Output Amplifier) All digital input pins (SDA, SCL, LDAC) are tied to "High", Output pins are unloaded, code = 0x000. The power-up ramp rate measures the rise of VDD over time. This parameter is ensured by design and not 100% tested. This parameter is ensured by characterization and not 100% tested. Test code range: 100 - 4000 codes, VREF = VDD, VDD = 5.5V. Time delay to settle to a new reference when switching from external to internal reference or vice versa. This parameter is indirectly tested by Offset and Gain error testing. Within 1/2 LSB of the final value when code changes from 1/4 of to 3/4 of full scale. This time delay is measured from the falling edge of ACK pulse in I2C command to the beginning of VOUT. This time delay is not included in the output settling time specification. DS22187A-page 4 (c) 2009 Microchip Technology Inc. MCP4728 www..com TABLE 1-1: ELECTRICAL CHARACTERISTICS (CONTINUED) Electrical Specifications: Unless otherwise indicated, all parameters apply at VDD = + 2.7V to 5.5V, VSS = 0V, RL = 5 k, CL = 100 pF, GX = 1, TA = -40C to +125C. Typical values are at +25C, VIH = VDD, VIL = VSS. Parameter Full Scale Range (Note 7) Symbol FSR Min -- -- -- Output Voltage Settling Time Analog Output Time Delay from Power-Down Mode Time delay to settle to new reference (Note 4) Power Supply Rejection Capacitive Load Stability Slew Rate Phase Margin Short Circuit Current TSETTLING TdExPD TdREF -- -- -- -- PSRR CL SR -- -- -- -- -- Typical VDD VREF 2 * VREF 6 4.5 26 44 -57 -- 0.55 66 15 Max -- -- -- -- -- -- -- -- 1000 -- -- 24 Units V V V s s s s dB pF V/s Degree CL = 400 pF, RL = () mA VDD = 5V, All VOUT Pins = Grounded. Tested at room temperature. (Note 4) Normal mode Power-Down Mode 1 (PD1:PD0 = 0:1), VOUT to VSS Power-Down Mode 2 (PD1:PD0 = 1:0), VOUT to VSS Power-Down Mode 3 (PD1:PD0 = 1:1), VOUT to VSS 1 LSB code change around major carry (from 7FFh to 800h) Conditions VREF = VDD FSR = from 0.0V to VDD VREF = Internal, Gx =1, FSR = from 0.0 V to VREF VREF = Internal, Gx =2, FSR = from 0.0V to 2*VREF (Note 8) VDD = 5V, (Note 4), (Note 9) From External to Internal Reference From Internal to External Reference VDD = 5V 10%, VREF = Internal RL = 5 k, No Oscillation, (Note 4) pM ISC Short Circuit Current Duration DC Output Impedance (Note 4) TSC_DUR ROUT -- -- -- -- -- Infinite 1 1 100 500 -- -- -- -- -- hours k k k Dynamic Performance (Note 4) Major Code Transition Glitch Digital Feedthrough Analog Crosstalk DAC-to-DAC Crosstalk Note 1: 2: 3: 4: 5: 6: 7: 8: 9: -- -- -- -- 45 <10 <10 <10 -- -- -- -- nV-s nV-s nV-s nV-s All digital input pins (SDA, SCL, LDAC) are tied to "High", Output pins are unloaded, code = 0x000. The power-up ramp rate measures the rise of VDD over time. This parameter is ensured by design and not 100% tested. This parameter is ensured by characterization and not 100% tested. Test code range: 100 - 4000 codes, VREF = VDD, VDD = 5.5V. Time delay to settle to a new reference when switching from external to internal reference or vice versa. This parameter is indirectly tested by Offset and Gain error testing. Within 1/2 LSB of the final value when code changes from 1/4 of to 3/4 of full scale. This time delay is measured from the falling edge of ACK pulse in I2C command to the beginning of VOUT. This time delay is not included in the output settling time specification. (c) 2009 Microchip Technology Inc. DS22187A-page 5 MCP4728 www..com TABLE 1-1: ELECTRICAL CHARACTERISTICS (CONTINUED) Electrical Specifications: Unless otherwise indicated, all parameters apply at VDD = + 2.7V to 5.5V, VSS = 0V, RL = 5 k, CL = 100 pF, GX = 1, TA = -40C to +125C. Typical values are at +25C, VIH = VDD, VIL = VSS. Parameter Digital Interface Output Low Voltage Schmitt Trigger Low Input Threshold Voltage Schmitt Trigger High Input Threshold Voltage Input Leakage Pin Capacitance EEPROM EEPROM Write Time Data Retention LDAC Input LDAC Low Time Note 1: 2: 3: 4: 5: 6: 7: 8: 9: TLDAC 210 -- -- ns Updates analog outputs (Note 3) All digital input pins (SDA, SCL, LDAC) are tied to "High", Output pins are unloaded, code = 0x000. The power-up ramp rate measures the rise of VDD over time. This parameter is ensured by design and not 100% tested. This parameter is ensured by characterization and not 100% tested. Test code range: 100 - 4000 codes, VREF = VDD, VDD = 5.5V. Time delay to settle to a new reference when switching from external to internal reference or vice versa. This parameter is indirectly tested by Offset and Gain error testing. Within 1/2 LSB of the final value when code changes from 1/4 of to 3/4 of full scale. This time delay is measured from the falling edge of ACK pulse in I2C command to the beginning of VOUT. This time delay is not included in the output settling time specification. TWRITE -- -- 25 200 50 -- ms Years EEPROM write time At +25C, (Note 3) VOL VIL -- -- -- VIH 0.7VDD -- -- -- -- 0.4 0.3VDD 0.2VDD -- V V V V IOL = 3 mA SDA and RDY/BSY pins VDD > 2.7V. SDA, SCL, LDAC pins VDD 2.7V. SDA, SCL, LDAC pins SDA, SCL, LDAC pins Symbol Min Typical Max Units Conditions ILI CPIN -- -- -- -- 1 3 A pF SCL = SDA = LDAC = VDD, SCL = SDA = LDAC = VSS (Note 4) DS22187A-page 6 (c) 2009 Microchip Technology Inc. MCP4728 www..com THIGH TRSCL TFSCL SCL TSU:STA TLOW SDA TSP THD:STA THD:DAT TSU:DAT 0.3VDD TSU:STO TBUF 0.7VDD TFSDA TAA TRSDA FIGURE 1-1: I2C Bus Timing Data. LDAC 0.7VDD 0.3VDD TLDAC VOUT (UDAC = 1) No Update Update FIGURE 1-2: LDAC Pin Timing vs. VOUT Update. (c) 2009 Microchip Technology Inc. DS22187A-page 7 MCP4728 www..com TABLE 1-2: I2C SERIAL TIMING SPECIFICATIONS Electrical Specifications: Unless otherwise specified, all limits are specified for TA = -40 to +125C, VSS = 0V, Standard and Fast Mode: VDD = +2.7V to +5.5V High Speed Mode: VDD = +4.5V to +5.5V. Parameters Clock Frequency Sym fSCL Min 0 0 0 0 Bus Capacitive Loading Cb -- -- -- -- Start Condition Setup Time (Start, Repeated Start) TSU:STA Typ -- -- -- -- -- -- -- -- Max 100 400 1.7 3.4 400 400 400 100 -- Units kHz kHz MHz MHz pF pF pF pF ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Conditions Standard Mode Cb = 400 pF, 2.7V - 5.5V Fast Mode Cb = 400 pF, 2.7V - 5.5V High Speed Mode 1.7 Cb = 400 pF, 4.5V - 5.5V High Speed Mode 3.4 Cb = 100 pF, 4.5V - 5.5V Standard Mode 2.7V - 5.5V Fast Mode 2.7V - 5.5V High Speed Mode 1.7 4.5V - 5.5V High Speed Mode 3.4 4.5V - 5.5V Standard Mode Fast Mode High Speed Mode 1.7 High Speed Mode 3.4 Standard Mode Fast Mode High Speed Mode 1.7 High Speed Mode 3.4 Standard Mode Fast Mode High Speed Mode 1.7 High Speed Mode 3.4 Standard Mode Fast Mode High Speed Mode 1.7 High Speed Mode 3.4 Standard Mode Fast Mode High Speed Mode 1.7 High Speed Mode 3.4 4700 600 160 160 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Start Condition Hold Time THD:STA 4000 600 160 160 Stop Condition Setup Time TSU:STO 4000 600 160 160 Clock High Time THIGH 4000 600 120 60 Clock Low Time TLOW 4700 1300 320 160 Note 1: 2: 3: 4: 5: This parameter is ensured by characterization and is not 100% tested. After a Repeated Start condition or an Acknowledge bit. If this parameter is too short, it can create an unintentional Start or Stop condition to other devices on the I2C bus line. If this parameter is too long, the Data Input Setup (TSU:DAT) or Clock Low time (TLOW) can be affected. Data Input: This parameter must be longer than tSP. Data Output: This parameter is characterized, and tested indirectly by testing TAA parameter. This specification is not a part of the I2C specification. This specification is equivalent to the Data Hold Time (THD:DAT) plus SDA Fall (or rise) time: TAA = THD:DAT + TFSDA (OR TRSDA). Time between Start and Stop conditions. DS22187A-page 8 (c) 2009 Microchip Technology Inc. MCP4728 www..com TABLE 1-2: I2C SERIAL TIMING SPECIFICATIONS (CONTINUED) Electrical Specifications: Unless otherwise specified, all limits are specified for TA = -40 to +125C, VSS = 0V, Standard and Fast Mode: VDD = +2.7V to +5.5V High Speed Mode: VDD = +4.5V to +5.5V. Parameters SCL Rise Time (Note 1) Sym TRSCL Min -- 20 + 0.1Cb 20 20 10 10 Typ -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 50 10 10 Max 1000 300 80 160 40 80 1000 300 80 40 300 300 160 80 300 300 160 80 -- -- -- -- 3450 900 70 150 3750 1200 150 310 -- -- -- -- -- -- -- -- Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Conditions Standard Mode Fast Mode High Speed Mode 1.7 High Speed Mode 1.7 (Note 2) High Speed Mode 3.4 High Speed Mode 3.4 (Note 2) Standard Mode Fast Mode High Speed Mode 1.7 High Speed Mode 3.4 Standard Mode Fast Mode High Speed Mode 1.7 High Speed Mode 3.4 Standard Mode Fast Mode High Speed Mode 1.7 High Speed Mode 3.4 Standard Mode Fast Mode High Speed Mode 1.7 High Speed Mode 3.4 Standard Mode Fast Mode High Speed Mode 1.7 High Speed Mode 3.4 Standard Mode Fast Mode High Speed Mode 1.7 High Speed Mode 3.4 Standard Mode Fast Mode High Speed Mode 1.7 High Speed Mode 3.4 Standard Mode, (Not Applicable) Fast Mode High Speed Mode 1.7 High Speed Mode 3.4 SDA Rise Time (Note 1) TRSDA -- 20 + 0.1Cb 20 10 SCL Fall Time (Note 1) TFSCL -- 20 + 0.1Cb 20 10 SDA Fall Time (Note 1) TFSDA -- 20 + 0.1Cb 20 10 Data Input Setup Time TSU:DAT 250 100 10 10 Data Hold Time (Input, Output) (Note 3) THD:DAT 0 0 0 0 Output Valid from Clock (Note 4) TAA 0 0 0 0 Bus Free Time (Note 5) TBUF 4700 1300 -- -- Input Filter Spike Suppression (SDA and SCL) (Not Tested) TSP -- -- -- -- Note 1: 2: 3: 4: 5: This parameter is ensured by characterization and is not 100% tested. After a Repeated Start condition or an Acknowledge bit. If this parameter is too short, it can create an unintentional Start or Stop condition to other devices on the I2C bus line. If this parameter is too long, the Data Input Setup (TSU:DAT) or Clock Low time (TLOW) can be affected. Data Input: This parameter must be longer than tSP. Data Output: This parameter is characterized, and tested indirectly by testing TAA parameter. This specification is not a part of the I2C specification. This specification is equivalent to the Data Hold Time (THD:DAT) plus SDA Fall (or rise) time: TAA = THD:DAT + TFSDA (OR TRSDA). Time between Start and Stop conditions. (c) 2009 Microchip Technology Inc. DS22187A-page 9 MCP4728 www..com TABLE 1-3: TEMPERATURE CHARACTERISTICS Symbol TA TA TA JA Min -40 -40 -65 -- Typical -- -- -- 202 Max +125 +125 +150 -- Units C C C C/W Conditions Electrical Specifications: Unless otherwise indicated, VDD = +2.7V to +5.5V, VSS = GND. Parameters Temperature Ranges Specified Temperature Range Operating Temperature Range Storage Temperature Range Thermal Package Resistances Thermal Resistance, 10L-MSOP DS22187A-page 10 (c) 2009 Microchip Technology Inc. MCP4728 www..com 2.0 Note: TYPICAL PERFORMANCE CURVES The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore, outside the warranted range. Note: Unless otherwise indicated, TA = -40C to +125C, VDD = +5.0V, VSS = 0V, RL = 5 k, CL = 100 pF. 6 4 INL (LSB) DNL(LSB) 2 0 0.3 0.2 0.1 0 VDD = 5.5V, VREF = Internal, Gain = x1 VDD = 5.5V, VREF = Internal, Gain = x1 -2 -4 -6 0 1024 2048 Code 3072 4096 -0.1 -0.2 0 1024 2048 Code 3072 4096 FIGURE 2-1: 6 4 INL vs. Code (TA = +25C). VDD = 5.5V, VREF = Internal, Gain = x2 FIGURE 2-4: 0.3 0.2 DNL (LSB) 0.1 0 -0.1 -0.2 DNL vs. Code (TA = +25C). VDD = 5.5V, VREF = Internal, Gain = x2 INL (LSB) 2 0 -2 -4 -6 0 1024 2048 Code 3072 4096 0 1024 2048 Code 3072 4096 FIGURE 2-2: 6 4 INL vs. Code (TA = +25C). FIGURE 2-5: 0.2 DNL vs. Code (TA = +25C). VDD = 5.5V, VREF = VDD VDD = 5.5V, VREF = VDD 0.15 DNL (LSB) 0 1024 2048 Code 3072 4096 0.1 0.05 0 INL (LSB) 2 0 -2 -4 -6 -0.05 -0.1 0 1024 2048 Code 3072 4096 FIGURE 2-3: INL vs. Code (TA = +25C). FIGURE 2-6: DNL vs. Code (TA = +25C). (c) 2009 Microchip Technology Inc. DS22187A-page 11 MCP4728 www..com Note: Unless otherwise indicated, TA = -40C to +125C, VDD = +5.0V, VSS = 0V, RL = 5 k, CL = 100 pF. 6 4 DNL (LSB) 0.4 0.3 0.2 0.1 0 VDD = 2.7V, VREF = Internal, Gain = x1 VDD = 2.7V, VREF = Internal, Gain = x1 INL (LSB) 2 0 -2 -4 -6 0 1024 2048 Code 3072 4096 -0.1 -0.2 0 1024 2048 Code 3072 4096 FIGURE 2-7: 6 4 INL vs. Code (TA = +25C). VDD = 2.7V, VREF = VDD FIGURE 2-10: 0.4 0.3 DNL (LSB) 0.2 0.1 0 DNL vs. Code (TA = +25C). VDD = 2.7V, VREF = VDD INL (LSB) 2 0 -2 -4 -6 0 1024 2048 Code 3072 4096 -0.1 -0.2 0 1024 2048 Code 3072 4096 FIGURE 2-8: 6 4 2 INL (LSB) 0 -2 -4 -6 -8 -10 0 1024 -40 C o INL vs. Code (TA = +25C). VDD = 5.5V, VREF = Internal, Gain = x1 +85C FIGURE 2-11: 0.4 0.3 DNL(LSB) 0.2 0.1 0 DNL vs. Code (TA = +25C). VDD = 5.5V, VREF = Internal, Gain = x1 +25 C o +125 C o -0.1 -0.2 +125oC - 40oC to +85oC 2048 Code 3072 4096 0 1024 2048 Code 3072 4096 FIGURE 2-9: Temperature. INL vs. Code and FIGURE 2-12: Temperature. DNL vs. Code and DS22187A-page 12 (c) 2009 Microchip Technology Inc. MCP4728 www..com Note: Unless otherwise indicated, TA = -40C to +125C, VDD = +5.0V, VSS = 0V, RL = 5 k, CL = 100 pF. 6 4 2 INL (LSB) 0 -2 -4 -6 -8 -10 0 1024 2048 Code 3072 4096 125oC - 40 C 25 C o o VDD = 5.5V, VREF = Internal, Gain = x2 85 C o 0.4 0.3 0.2 DNL (LSB) 0.1 0 -0.1 -0.2 -0.3 0 +125oC VDD = 5.5V, VREF = Internal, Gain = x2 - 40oC to +85oC 1024 2048 Code 3072 4096 FIGURE 2-13: Temperature. 6 4 2 INL (LSB) 0 -2 -4 -6 -8 -10 0 125 C o INL vs. Code and FIGURE 2-16: Temperature. 0.5 0.4 0.3 DNL (LSB) 0.2 0.1 0 DNL vs. Code and VDD = 2.7V, VREF = Internal, Gain = x1 VDD = 2.7V, VREF = Internal, Gain = 1X - 40oC 25oC 85oC -0.1 -0.2 -0.3 +125oC - 40oC to +85oC 1024 2048 Code 3072 4096 0 1024 2048 Code 3072 4096 FIGURE 2-14: Temperature. 6 4 INL vs. Code and FIGURE 2-17: Temperature. 0.4 0.3 DNL vs. Code and VDD = 5.5V, VREF = VDD 85oC VDD = 5.5V, VREF = VDD DNL (LSB) INL (LSB) 2 0 -2 -4 0.2 0.1 0 +125oC - 40oC to +85oC - 40oC 125oC 25oC -0.1 -0.2 -6 0 1024 2048 Code 3072 4096 0 1024 2048 Code 3072 4096 FIGURE 2-15: Temperature. INL vs. Code and FIGURE 2-18: Temperature. DNL vs. Code and (c) 2009 Microchip Technology Inc. DS22187A-page 13 MCP4728 www..com Note: Unless otherwise indicated, TA = -40C to +125C, VDD = +5.0V, VSS = 0V, RL = 5 k, CL = 100 pF. 6 4 2 DNL (LSB) INL (LSB) 0 125oC 25oC VDD = 2.7V, VREF = VDD - 40 C o 0.5 0.4 0.3 0.2 0.1 0 VDD = 2.7V, VREF = VDD 85oC -2 -4 -6 -8 0 1024 2048 Code -0.1 -0.2 -0.3 3072 4096 0 +125oC - 40oC to +85oC 1024 2048 Code 3072 4096 FIGURE 2-19: Temperature. -10 Full Scale Error (mV) -20 INL vs. Code and FIGURE 2-22: Temperature. 6 Offset Error (mV) DNL vs. Code and VDD = 2.7V, Gain = 1 5 4 3 2 1 VDD = 5.5V, Gain = 2 VDD = 5.5V, Gain = 1 -30 -40 VDD = 5.5V, Gain = 2 VDD = 5.5V, Gain = 1 VDD = 2.7V, Gain = 1 -50 -40 -25 -10 5 20 35 50 65 80 Temperature (oC) 95 110 125 0 -40 -25 -10 5 20 35 50 65 80 Temperature (oC) 95 110 125 FIGURE 2-20: Full Scale Error vs. Temperature (Code = FFFh, VREF = Internal). 50 Full Scale Error (mV) VDD = 5.5V, Gain = 1 FIGURE 2-23: Zero Scale Error vs. Temperature (Code = 000h, VREF = Internal). 4 3 2 VDD = 2.7V 40 30 VDD = 2.7V, Gain = 1 Offset Error (mV) VDD = 5.5V 20 1 0 10 -40 -25 -10 5 20 35 50 65 80 Temperature (oC) 95 110 125 -40 -25 -10 5 20 35 50 65 o 80 95 110 125 Temperature ( C) FIGURE 2-21: Full Scale Error vs. Temperature (Code = FFFh, VREF = VDD). FIGURE 2-24: Zero Scale Error vs. Temperature (Code = 000h, VREF = VDD). DS22187A-page 14 (c) 2009 Microchip Technology Inc. MCP4728 www..com Note: Unless otherwise indicated, TA = -40C to +125C, VDD = +5.0V, VSS = 0V, RL = 5 k, CL = 100 pF. VOUT (2V/Div) VOUT (2V/Div) LDAC Time (2/s/Div LDAC Time (2/s/Div FIGURE 2-25: Full Scale Settling Time (VREF = VDD, VDD = 5V, UDAC = 1, Code Change: 000h to FFFh). FIGURE 2-28: Full Scale Settling Time (VREF = VDD, VDD = 5V, UDAC = 1, Code Change: FFFh to 000h ). VOUT (2V/Div) VOUT (2V/Div) LDAC Time (2/s/Div LDAC Time (2/s/Div FIGURE 2-26: Half Scale Settling Time (VREF = VDD, VDD = 5V, UDAC = 1, Code Change: 000h to 7FFh). FIGURE 2-29: Half Scale Settling Time (VREF = VDD, VDD = 5V, UDAC = 1, Code Change: FFFh to 000h). VOUT (2V/Div) VOUT (2V/Div) LDAC Time (2/s/Div LDAC Time (2/s/Div FIGURE 2-27: Full Scale Settling Time (VREF = Internal, VDD = 5V, UDAC = 1, Code Change: 000h to FFFh). FIGURE 2-30: Full Scale Settling Time (VREF = Internal, VDD = 5V, UDAC = 1, Code Change: FFFh to 000h). (c) 2009 Microchip Technology Inc. DS22187A-page 15 MCP4728 www..com Note: Unless otherwise indicated, TA = -40C to +125C, VDD = +5.0V, VSS = 0V, RL = 5 k, CL = 100 pF. VOUT (1V/Div) VOUT (1V/Div) LDAC Time (2/s/Div LDAC Time (2 s/Div FIGURE 2-31: Half Scale Settling Time (VREF = Internal, VDD = 5V, UDAC = 1, Code Change: 000h to 7FFh). FIGURE 2-34: Half Scale Settling Time (VREF = Internal, VDD = 5V, UDAC = 1), Code Change: 7FFh to 000h. VOUT (1V/Div) VOUT (2V/Div) TdExPD Time (5/s/Div CLK Last ACK CLK pulse CLK TdExPD Time (5 s/Div Last ACK CLK pulse FIGURE 2-32: Exiting Power Down Mode (Code : FFFh, VREF = Internal, VDD = 5V, for all Channels.). Discharging Time due to VOUT (1V/Div) internal pull-down resistor (500 k) FIGURE 2-35: Exiting Power Down Mode (Code : FFFh, VREF = VDD, VDD = 5V, for all Channels). Discharging Time due to internal pull-down resistor (500 k) VOUT (2V/Div) Time (10/s/Div CLK Last ACK CLK pulse CLK Time (20/s/Div Last ACK CLK pulse FIGURE 2-33: Entering Power Down Mode (Code : FFFh, VREF = Internal, VDD = 5V, PD1= PD0 = 1, No External Load). FIGURE 2-36: Entering Power Down Mode (Code : FFFh, VREF = VDD, VDD = 5V, PD1= PD0 = 1, No External Load). DS22187A-page 16 (c) 2009 Microchip Technology Inc. MCP4728 www..com Note: Unless otherwise indicated, TA = -40C to +125C, VDD = +5.0V, VSS = 0V, RL = 5 k, CL = 100 pF. VOUT (2V/Div) VOUT (50 mV/Div) Time (10/s/Div CLK Last ACK CLK pulse Time (2/s/Div FIGURE 2-37: VOUT Time Delay when VREF changes from Internal Reference to VDD. FIGURE 2-40: Code Change Glitch (VREF = External, VDD = 5V, No External Load), Code Change: 800h to 7FFh. VOUT (2V/Div) VOUT (50 mV/Div) Time (2/s/Div Time (10/s/Div CLK Last ACK CLK pulse FIGURE 2-38: VOUT Time Delay when VREF changes from VDD to Internal Reference. FIGURE 2-41: Code Change Glitch (VREF = Internal, VDD = 5V, Gain = 1, No External Load), Code Change: 800h to 7FFh. 6 5 4 VOUT (V) VDD = 5V VREF = VDD Code = FFFh VOUT at Channel D (5V/Div) LDAC VOUT at Channel A (100 mV/Div) Time (5/s/Div 3 2 1 0 0 1 2 3 Load Resistance (k) 4 5 FIGURE 2-39: Channel Cross Talk (VREF = VDD, VDD = 5V). FIGURE 2-42: VOUT vs. Resistive Load. (c) 2009 Microchip Technology Inc. DS22187A-page 17 MCP4728 www..com Note: Unless otherwise indicated, TA = -40C to +125C, VDD = +5.0V, VSS = 0V, RL = 5 k, CL = 100 pF. 1000 VDD = 5.0V All Channels On 3 Channels On 1000 800 IDD_EXT (A) 600 VDD = 5.0V All Channels On 3 Channels On 800 IDD_INT (A) 600 2 Channels On 2 Channels On 400 200 0 -40 -25 -10 5 20 35 50 65 80 95 110 125 Temperature (oC) 1 Channel On 400 1 Channel On 200 0 -40 -25 -10 5 20 35 50 65 80 95 110 125 Temperature (oC) FIGURE 2-43: IDD vs. Temperature (VREF = VDD, VDD = 5V, Code = FFFh). 800 600 IDD_EXT (A) 3 Channels On FIGURE 2-46: IDD vs. Temperature (VREF = Internal, VREF = 5V, Code = FFFh). 1000 VDD = 2.7V All Channels On V DD = 2.7V 800 IDD_INT (A) 600 400 200 0 All Channels On 3 Channels On 2 Channels On 1 Channel On 400 2 Channels On 200 1 Channel On 0 -40 -25 -10 5 20 35 50 65 80 95 110 125 Temperature (oC) -40 -25 -10 5 20 35 50 65 80 95 110 125 Temperature (oC) FIGURE 2-44: IDD vs. Temperature (VREF = VDD, VDD = 2.7V, Code = FFFh). 900 800 IDD_EXT (A) 700 VDD = 3.3V All Channels On V DD = 5V VDD = 5.5V FIGURE 2-47: IDD vs. Temperature (VREF = Internal, VDD = 2.7V, Code = FFFh). 900 800 IDD_INT (A) 700 600 VDD = 5.5V All Channels On VDD = 5V VDD = 4.5V VDD = 4.5V VDD = 3.3V VDD = 2.7V 600 VDD = 2.7V 500 -40 -25 -10 5 20 35 50 65 80 95 110 125 Temperature (oC) 500 -40 -25 -10 5 20 35 50 65 o 80 95 110 125 Temperature ( C) FIGURE 2-45: IDD vs. Temperature (VREF = VDD, All channels are in Normal Mode, Code = FFFh). FIGURE 2-48: IDD vs. Temperature (VREF = Internal , All Channels are in Normal Mode, Code = FFFh). DS22187A-page 18 (c) 2009 Microchip Technology Inc. MCP4728 www..com Note: Unless otherwise indicated, TA = -40C to +125C, VDD = +5.0V, VSS = 0V, RL = 5 k, CL = 100 pF. 60 50 V DD = 4.5V 6 All Channels Off VDD = 5V VDD = 5.5V Code = 000h 5 VOUT (V) 4 3 2 1 0 IDDP_INT (A) 40 30 VDD = 3.3V VDD = 2.7V 20 -40 -25 -10 5 20 35 50 65 o Temperature ( C) 80 95 110 125 0 2 4 6 8 10 12 14 Sink Current (mA) FIGURE 2-49: IDD vs. Temperature (VREF = Internal , All Channels are in Powered Down). 6 5 VOUT (V) 4 3 2 1 0 0 2 4 6 8 10 12 14 16 Current (mA) FIGURE 2-51: Sink Current Capability (VREF = VDD, Code = 000h). Code = FFFh FIGURE 2-50: Source Current Capability (VREF = VDD, Code = FFFh). (c) 2009 Microchip Technology Inc. DS22187A-page 19 MCP4728 www..com NOTES: DS22187A-page 20 (c) 2009 Microchip Technology Inc. MCP4728 www..com 3.0 PIN DESCRIPTIONS PIN FUNCTION TABLE Pin Type P OI OI/OO ST Supply Voltage I2C Serial Clock Input. (Note 1) I2C Serial Data Input and Output. (Note 1) This pin is used for two purposes: (a) Synchronization Input. It is used to transfer the contents of the DAC input registers to the output registers (VOUT). (b) Select the device for reading and writing I2C address bits. (Note 2) This pin is a status indicator of EEPROM programming activity. An external pull-up resistor (about 100 k) is needed from RDY/BSY pin to VDD line. (Note 1) Buffered analog voltage output of channel A. The output amplifier has rail-to-rail operation. Buffered analog voltage output of channel B. The output amplifier has rail-to-rail operation. Buffered analog voltage output of channel C. The output amplifier has rail-to-rail operation. Buffered analog voltage output of channel D. The output amplifier has rail-to-rail operation. Ground reference. Function VDD SCL SDA LDAC The descriptions of the pins are listed in Table 3-1. TABLE 3-1: Pin No. 1 2 3 4 Name 5 6 7 8 9 10 RDY/BSY VOUT A VOUT B VOUT C VOUT D VSS OO AO AO AO AO P Legend: P = Power, OI = Open-Drain Input, OO = Open-Drain Output, ST = Schmitt Trigger Input Buffer, AO = Analog Output Note 1: This pin needs an external pull-up resistor from VDD line. 2: This pin can be driven by MCU. 3.1 Analog Output Voltage Pins (VOUTA, VOUTB, VOUTC, VOUTD) 3.2 Supply Voltage Pins (VDD, VSS) The device has four analog voltage output (VOUT) pins. Each output is driven by its own output buffer with a gain of 1 or 2 depending on the gain and VREF selection bit settings. In normal mode, the DC impedance of the output pin is about 1. In Power-Down mode, the output pin is internally connected to 1 k, 100 k, or 500 k, depending on the Power-Down selection bit settings. The VOUT pin can drive up to 1000 pF of capacitive load. It is recommended to use a load with RL greater than 5 k. VDD is the power supply pin for the device. The voltage at the VDD pin is used as the power supply input as well as the DAC external reference. The power supply at the VDD pin should be as clean as possible for a good DAC performance. It is recommended to use an appropriate bypass capacitor of about 0.1 F (ceramic) to ground. An additional 10 F capacitor (tantalum) in parallel is also recommended to further attenuate high frequency noise present in application boards. The supply voltage (VDD) must be maintained in the 2.7V to 5.5V range for specified operation. VSS is the ground pin and the current return path of the device. The user must connect the VSS pin to a ground plane through a low impedance connection. If an analog ground path is available in the application PCB (printed circuit board), it is highly recommended that the VSS pin be tied to the analog ground path or isolated within an analog ground plane of the circuit board. (c) 2009 Microchip Technology Inc. DS22187A-page 21 MCP4728 www..com 3.3 Serial Data Pin (SDA) 2 3.5 LDAC Pin SDA is the serial data pin of the I C interface. The SDA pin is used to write or read the DAC register and EEPROM data. Except for start and stop conditions, the data on the SDA pin must be stable during the high duration of the clock pulse. The High or Low state of the SDA pin can only change when the clock signal on the SCL pin is Low. The SDA pin is an open-drain N-channel driver. Therefore, it needs a pull-up resistor from the VDD line to the SDA pin. Refer to Section 5.0 "I2C Serial Interface Communications" for more details of the I2C Serial Interface communication. This pin can be driven by an external control device such as an MCU I/O pin. This pin is used (a) to transfer the contents of the input registers to their corresponding DAC output registers and (b) to select a device of interest when reading or writing I2C address bits. See sections Section 5.4.4 "General call Read Address Bits" and Section 5.6.8 "Write Command: Write I2C Address bits (C2=0, C1=1, C0=1)" for more details of the reading and writing the device I2C address bits, respectively. When the logic status of the LDAC pin changes from "High" to "Low", the contents of all input registers (Channels A - D) are transferred to their corresponding output registers and all analog voltage outputs are updated simultaneously. If this pin is permanently tied to "Low", the content of the input register is transferred to its output register (VOUT) immediately at the last input data byte's acknowledge pulse. The user can also use the UDAC bit instead. However, the UDAC bit updates a selected channel only. See Section 4.8 "Output Voltage Update" for more information on the LDAC pin and UDAC bit functions. 3.4 Serial Clock Pin (SCL) SCL is the serial clock pin of the I2C interface. The MCP4728 device acts only as a slave and the SCL pin accepts only external input serial clocks. The input data from the Master device is shifted into the SDA pin on the rising edges of the SCL clock and output from the MCP4728 occurs at the falling edges of the SCL clock. The SCL pin is an open-drain N-channel driver. Therefore, it needs a pull-up resistor from the VDD line to the SCL pin. Refer to Section 5.0 "I2C Serial Interface Communications" for more details of I2C Serial Interface communication. Typical range of the pull-up resistor value for SCL and SDA is from 5 k to 10 k for standard (100 kHz) and fast (400 kHz) modes, and less than 1 k for high speed mode (3.4 MHz). 3.6 RDY/BSY Status Indicator Pin This pin is a status indicator of EEPROM programming activity. This pin is "High" when the EEPROM has no programming activity and "Low" when the EEPROM is in programming mode. It goes "High" when the EEPROM program is completed. The RDY/BSY pin is an open-drain N-channel driver. Therefore, it needs a pull-up resistor (about 100 k) from the VDD line to the RDY/BSY pin. DS22187A-page 22 (c) 2009 Microchip Technology Inc. MCP4728 www..com 4.0 THEORY OF DEVICE OPERATION 4.2 Reset Conditions The MCP4728 device is a 12-bit 4-channel buffered voltage output DAC with non-volatile memory (EEPROM). The user can program the EEPROM with I2C address bits, configuration and DAC input data of each channel. The device has an internal charge pump circuit to provide the programming voltage of the EEPROM. When the device is first powered-up, it automatically loads the stored data in its EEPROM to the DAC input and output registers, and provides analog outputs with the saved settings immediately. This event does not require LDAC or UDAC bit condition. After the device is powered-up, the user can update the input registers using I2C write commands. The analog outputs can be updated with new register values if LDAC pin or UDAC bit is low. The DAC output of each channel is buffered with a low power and precision output amplifier. This amplifier provides a rail-to-rail output with low offset voltage and low noise. The device uses a resistor string architecture. The resistor ladder DAC can be driven from VDD or internal VREF depending on the reference selection. The user can select internal (2.048V) or external reference (VDD) for each DAC channel individually by software control. The VDD is used as the external reference. Each channel is controlled and operated independently. The device has a Power-Down mode feature. Most of the circuit in each powered down channel are turned off. Therefore, operating power can be saved significantly by putting any unused channel to the Power-Down mode. The device can be reset by two independent events: (a) by Power-On-Reset or (b) by I2C General Call Reset Command. Under the reset conditions, the device uploads the EEPROM data into both of the DAC input and output registers simultaneously. The analog output voltage of each channel is available immediately regardless of the LDAC and UDAC bit conditions. The factory default settings for the EEPROM prior to the device shipment are shown in Table 4-2. 4.3 Output Amplifier The DAC output is buffered with a low power precision amplifier. This amplifier provides low offset voltage and low noise, as well as rail-to-rail output. The output amplifier can drive the resistive and high capacitive loads without oscillation. The amplifier can provide a maximum load current of 24 mA which is enough for most of programmable voltage reference applications. Refer to Section 1.0 "Electrical Characteristics" for the specifications of the output amplifier. 4.3.1 PROGRAMMABLE GAIN BLOCK The rail-to-rail output amplifier of each channel has configurable gain option. When the internal voltage reference is selected, the output amplifier gain has two selection options: gain of 1 or gain of 2. When the external reference is selected (VREF = VDD), the gain of 2 option is disabled, and only the gain of 1 is used by default. 4.3.1.1 Resistive and Capacitive Loads 4.1 Power-On-Reset (POR) The device contains an internal Power-On-Reset (POR) circuit that monitors power supply voltage (VDD) during operation. This circuit ensures correct device start-up at system power-up and power-down events. If the power supply voltage is less than the POR threshold (VPOR = 2V, typical), all circuits are disabled and there will be no analog output. When the VDD increases above the VPOR, the device takes a reset state. During the reset period, each channel uploads all configuration and DAC input codes from EEPROM, and analog output (VOUT) will be available accordingly. This enables the device to return to the same state that it was at the last write to the EEPROM before it was powered off. The POR status is monitored by the POR status bit by using the I2C read command. See Figure 5-15 for the details of the POR status bit. The POR circuit is also powered off if all channels are powered down during the Power-Down mode. The analog output (VOUT) pin is capable of driving capacitive loads up to 1000 pF in parallel with 5 k load resistance. Figure 2-42 shows the VOUT vs. Resistive Load. (c) 2009 Microchip Technology Inc. DS22187A-page 23 MCP4728 www..com 4.4 DAC Input Registers and Non-Volatile EEPROM Memory TABLE 4-1: INPUT REGISTER MAP (VOLATILE) Each channel has its own volatile DAC input register and EEPROM. The details of the input registers and EEPROM are shown in Table 4-1 and Table 4-2, respectively. Configuration Bits DAC Input Data (12 bits) PD0 GX D11 D10 D9 D8 D7 D6 D5 (Note 2) D4 D3 D2 D1 D0 Bit Name Bit Function RDY /BSY A2 A1 A0 VREF DAC1 DAC0 PD1 Ref. DAC Channel Power-Down Gain I2C Address Bits Select Select Select (Note 2) (Note 2) (Note 2) (Note 2) (Note 1) (Note 2) CH. A CH. B CH. C CH. D Note 1: 2: EEPROM write status indication bit (flag). Loaded from EEPROM during power-up, or can be updated by the user. TABLE 4-2: EEPROM MEMORY MAP AND FACTORY DEFAULT SETTINGS Configuration Bits DAC Input Data (12 bits) PD0 GX Gain Select (Note 3) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 A2 A1 A0 VREF Ref. Select (Note 2) 1 1 1 1 PD1 Bit Name Bit Function I2C Address Bits (Note 1) 0 0 0 Power-Down Select CH. A CH. B CH. C CH. D 0 0 0 0 0 0 0 0 Note 1: 2: 3: Device I2C address bits. The user can also specify these bits during the device ordering process. The factory default setting is "000". These bits can be reprogrammed by the user using the I2C Address Write command. Voltage Reference Select: 0 = External VREF (VDD), 1 = Internal VREF (2.048V). Gain Select: 0 = Gain of 1, 1 = Gain of 2. DS22187A-page 24 (c) 2009 Microchip Technology Inc. MCP4728 www..com TABLE 4-3: Bit Name RDY/BSY CONFIGURATION BITS Functions This is a status indicator (flag) of EEPROM programming activity: 1 = EEPROM is not in programming mode 0 = EEPROM is in programming mode Note: RDY/BSY status can also be monitored at the RDY/BSY pin. Device I2C address bits. See Section 5.3 "MCP4728 Device Addressing" for more details. Voltage Reference Selection bit: 0 = VDD 1 = Internal voltage reference (2.048V) Note: Internal voltage reference circuit is turned off if all channels select external reference (VREF = VDD). DAC Channel Selection bits: 00 = Channel A 01 = Channel B 10 = Channel C 11 = Channel D Power-Down selection bits: 00 = Normal Mode 01 = VOUT is loaded with 1 k resistor to ground. Most of the channel circuits are powered off. 10 = VOUT is loaded with 100 k resistor to ground. Most of the channel circuits are powered off. 11 = VOUT is loaded with 500 k resistor to ground. Most of the channel circuits are powered off. Note: See Table 4-7 and Figure 4-1 for more details. Gain selection bit: 0 = x1 (gain of 1) 1 = x2 (gain of 2) Note: Applicable only when internal VREF is selected. If VREF = VDD, the device uses a gain of 1 regardless of the gain selection bit setting. DAC latch bit. Upload the selected DAC input register to its output register (VOUT): 0 = Upload. Output (VOUT) is updated. 1 = Do not upload. Note: UDAC bit affects the selected channel only. (A2, A1, A0) VREF DAC1, DAC0 PD1, PD0 GX UDAC (c) 2009 Microchip Technology Inc. DS22187A-page 25 MCP4728 www..com 4.5 Voltage Reference 4.7.1 OUTPUT VOLTAGE RANGE The device has a precision internal voltage reference which provides a nominal voltage of 2.048V. The user can select the internal voltage reference or VDD as the voltage reference source of each channel using the VREF configuration bit. The internal voltage reference circuit is turned off when all channels select VDD as their references. However, it stays turned on if any one of the channels selects the internal reference. The DAC output voltage range varies depending on the voltage reference selection. * When the internal reference (VREF=2.048V) is selected: VOUT = 0.000V to 2.048V * 4095/4096 for Gain of 1 = 0.000V to 4.096V * 4095/4096 for Gain of 2 * When the external reference (VREF=VDD) is selected: VOUT = 0.000V to VDD Note that the gain selection bit is not applicable for VREF = VDD. Gain of 1 is used regardless of the gain selection bit setting. 4.6 LSB Size The LSB is defined as the ideal voltage difference between two successive codes. LSB sizes of the MCP4728 device are shown in Table 4-4. TABLE 4-4: VREF Internal VREF (2.048V) VDD Note 1: LSB SIZES (EXAMPLE) Gain (GX) Selection x1 x2 LSB Size 0.5 mV 1 mV Condition 2.048V/4096 4.096V/4096 EQUATION 4-1: V OUT Where: VREF Dn Gx = = = INTERNAL REFERENCE ( V REF x D n ) = ------------------------------ G x V DD 4096 VOUT FOR VREF = x1 VDD/4096 (Note 1 LSB size varies with the VDD range. When VREF = VDD, the device uses GX = 1 by default. GX = 2 option is ignored. 2.048V for internal reference selection DAC input code Gain Setting EQUATION 4-2: 4.7 DAC Output Voltage V OUT = ---------------------------4096 Where: Dn = DAC input code VOUT FOR VREF = VDD ( V DD x D n ) Each channel has an independent output associated with its own configuration bit settings and DAC input code. When the internal voltage reference is selected (VREF = internal), it supplies the internal VREF voltage to the resistor string DAC of the channel. When the external reference (VREF=VDD) is selected, VDD is used for the channel's resistor string DAC. The VDD needs to be as clean as possible for accurate DAC performance. When the VDD is selected as the voltage reference, any variation or noises on the VDD line can directly affect on the DAC output. The analog output of each channel has a programmable gain block. The rail-to-rail output amplifier has a configurable gain of 1 or 2. But the gain of 2 is not applicable if VDD is selected for the voltage reference. The formula for the analog output voltage is given in Equation 4-1 and Equation 4-2. 4.8 Output Voltage Update The following events update the output registers (VOUT): a. b. c. d. LDAC pin to "Low": Updates all DAC channels. UDAC bit to "Low": Updates a selected channel only. General Call Software Update Command: Updates all DAC channels. Power-On-Reset or General Call Reset command: Both input and output registers are updated with EEPROM data. All channels are affected. 4.8.1 LDAC PIN AND UDAC BIT The user can use the LDAC pin or UDAC bit to upload the input DAC register to output DAC register (VOUT). However, the UDAC affects only the selected channel while the LDAC affects all channels. The UDAC bit is not used in the Fast Mode Writing. Table 4-5 shows the output update vs. LDAC pin and UDAC bit conditions. DS22187A-page 26 (c) 2009 Microchip Technology Inc. MCP4728 www..com TABLE 4-5: LDAC AND UDAC CONDITIONS VS. OUTPUT UPDATE DAC Output (VOUT) Update all DAC channel outputs. Update all DAC channel outputs. Update a selected DAC channel output. No update 0 1 0 1 LDAC Pin UDAC Bit 0 0 1 1 4.9 Analog Output Vs. DAC Input Code TABLE 4-6: DAC INPUT CODE VS. ANALOG OUTPUT (VOUT) VREF = VDD Gain Selection Ignored Nominal Output Voltage (V) VDD - 1 LSB VDD - 2 LSB 2 LSB 1 LSB 0 Table 4-6 shows an example of the DAC input data code vs. analog output. The MSB of the input data is always transmitted first and the format is unipolar binary. VREF = Internal (2.048 V) DAC Input Code Gain Selection x1 x2 111111111110 000000000010 000000000001 000000000000 Note 1: x1 x2 x1 x2 x1 x2 x1 x2 Nominal Output Voltage (V) (See Note 1) VREF - 1 LSB 2*VREF - 1 LSB VREF - 2 LSB 2*VREF - 2 LSB 2 LSB 2 LSB 1 LSB 1 LSB 0 0 111111111111 (a) LSB with gain of 1 = 0.5 mV, and (b) LSB with gain of 2 = 1 mV. (c) 2009 Microchip Technology Inc. DS22187A-page 27 MCP4728 www..com 4.10 Normal and Power-Down Modes Each channel has two modes of operation: (a) Normal mode where analog voltage is available and (b) Power-Down mode which turns off most of the internal circuits for power savings. The user can select the operating mode of each channel individually by setting the Power-Down selection bits (PD1 and PD0). For example, the user can select channel A for normal mode while selecting all other channels for power-down mode. See Section 5.6 "Write Commands for DAC Registers and EEPROM" for more details on the writing the power-down bits. Most of the internal circuit in the powered down channel are turned off. However, the internal voltage reference circuit is not affected by the Power-Down mode. The internal voltage reference circuit is turned off only if all channels select external reference (VREF = VDD). Device actions during Power-Down mode: * The powered down channel stays in a power saving condition by turning off most of its circuits. * No analog voltage output at the powered down channel. * The output (VOUT) pin of the powered down channel is switched to a known resistive load. The value of the resistive load is determined by the state of the Power-Down bits (PD1 and PD0). Table 4-7 shows the outcome of the Power-Down bit settings. * The contents of both the DAC registers and EEPROM are not changed. * Draws less than 40 nA (typical) when all four channels are powered down and VDD is selected as the voltage reference. Circuits that are not affected during Power-Down Mode: * The I2C serial interface circuits remain active in order to receive any command from the Master. * The internal voltage reference circuit stays turned-on if it is selected as reference by at least one channel. Exiting Power-Down Mode: The device exits Power-Down mode immediately by the following commands: * Any write command for normal mode. Only selected channel is affected. * I2C General Call Wake-Up Command. All channels are affected. * I2C General Call Reset Command. This is a conditional case. The device exits Power-Down mode depending on the Power-Down bit settings in EEPROM as the configuration bits and DAC input codes are uploaded from EEPROM. All channels are affected. When the DAC operation mode is changed from the Power-Down to normal mode, there will be a time delay until the analog output is available. Typical time delay for the output voltage is approximately 4.5 s. This time delay is measured from the acknowledge pulse of the I2C serial communication command to the beginning of the analog output (VOUT). This time delay is not included in the output settling time specification. See Section 2.0 "Typical Performance Curves" for more details. TABLE 4-7: PD1 0 0 1 1 Note 1: PD0 0 1 0 POWER-DOWN BITS Function Normal Mode 1 k resistor to ground (Note 1) 100 k resistor to ground (Note 1) 1 500 k resistor to ground (Note 1) In Power-Down mode: VOUT is off and most of internal circuits in the selected channel are disabled. VOUT OP Amp Power-Down Control Circuit 1 k 100 k 500 k Resistor String DAC Resistive Load FIGURE 4-1: Output Stage for Power-Down Mode. DS22187A-page 28 (c) 2009 Microchip Technology Inc. MCP4728 www..com 5.0 I2C SERIAL INTERFACE COMMUNICATIONS mode and can communicate at up to 3.4 Mbit/s on SDA and SCL lines. The device will switch out of the HS mode on the next STOP condition. For more information on the HS mode, or other I2C modes, please refer to the Philips I2C specification. The MCP4728 device uses a two-wire I2C serial interface. When the device is connected to the I2C bus line, the device works as a slave device. The device supports standard, fast and high speed modes. The following sections describes how to communicate the MCP4728 device using the I2C serial interface commands. 5.2 I2C BUS CHARACTERISTICS The specification of the I2C serial communication defines the following bus protocol: * Data transfer may be initiated only when the bus is not busy. * During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in the data line while the clock line is HIGH will be interpreted as a START or STOP condition. Accordingly, the following bus conditions have been defined using Figure 5-1. 5.1 Overview of I2C Serial Interface Communications An example of hardware connection diagram is shown in Figure 7-1. A device that sends data onto the bus is defined as transmitter, and a device receiving data as receiver. The bus has to be controlled by a master (MCU) device which generates the serial clock (SCL), controls the bus access and generates the START and STOP conditions. Both master (MCU) and slave (MCP4728) can operate as transmitter or receiver, but the master device determines which mode is activated. Communication is initiated by the master (MCU) which sends the START bit, followed by the slave (MCP4728) address byte. The first byte transmitted is always the slave (MCP4728) address byte, which contains the device code (1100), the address bits (A2, A1, A0), and the R/W bit. The device code for the MCP4728 device is 1100, and the address bits are user-writable. When the MCP4728 device receives a read command (R/W = 1), it transmits the contents of the DAC input registers and EEPROM sequentially. When writing to the device (R/W = 0), the device will expect write command type bits in the following byte. The reading and various writing commands are explained in the following sections. The MCP4728 device supports all three I2C serial communication operating modes: * Standard Mode: bit rates up to 100 kbit/s * Fast Mode: bit rates up to 400 kbit/s * High Speed Mode (HS mode): bit rates up to 3.4 Mbit/s Refer to the Philips I2C document for more details of the I2C specifications. 5.2.1 BUS NOT BUSY (A) Both data and clock lines remain HIGH. 5.2.2 START DATA TRANSFER (B) A HIGH to LOW transition of the SDA line while the clock (SCL) is HIGH determines a START condition. All commands must be preceded by a START condition. 5.2.3 STOP DATA TRANSFER (C) A LOW to HIGH transition of the SDA line while the clock (SCL) is HIGH determines a STOP condition. All operations must be ended with a STOP condition. 5.2.4 DATA VALID (D) The state of the data line represents valid data when, after a START condition, the data line is stable for the duration of the HIGH period of the clock signal. The data on the line must be changed during the LOW period of the clock signal. There is one clock pulse per bit of data. Each data transfer is initiated with a START condition and terminated with a STOP condition. 5.2.5 ACKNOWLEDGE 5.1.1 HIGH-SPEED (HS) MODE The I2C specification requires that a high-speed mode device must be `activated' to operate in high-speed (3.4 Mbit/s) mode. This is done by sending a special address byte of 00001XXX following the START bit. The XXX bits are unique to the high-speed (HS) mode Master. This byte is referred to as the high-speed (HS) Master Mode Code (HSMMC). The MCP4728 device does not acknowledge this byte. However, upon receiving this command, the device switches to HS Each receiving device, when addressed, is obliged to generate an acknowledge after the reception of each byte. The master device must generate an extra clock pulse which is associated with this acknowledge bit. The device that acknowledges, has to pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse. Of course, setup and hold times must be taken into account. During reads, a master must send an end of data to the slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave. (c) 2009 Microchip Technology Inc. DS22187A-page 29 MCP4728 www..com In this case, the slave (MCP4728) will leave the data line HIGH to enable the master to generate the STOP condition. (A) SCL (B) (D) (D) (C) (A) SDA START CONDITION DATA ADDRESS OR ACKNOWLEDGE ALLOWED TO CHANGE VALID STOP CONDITION FIGURE 5-1: Data Transfer Sequence On The Serial Bus. 5.3.1 PROGRAMMING OF I2C ADDRESS BITS 5.3 MCP4728 Device Addressing The address byte is the first byte received following the START condition from the master device. The first part of the address byte consists of a 4-bit device code which is set to 1100 for the MCP4728 device. The device code is followed by three I2C address bits (A2, A1, A0) which are programmable by the users. Although the three address bits are programmable at the user's application PCB, the user can also specify the address bits during the product ordering process. If there is no user's request, the factory default setting of the three address bits is "000" which is programmed into the EEPROM. The three address bits allows eight unique addresses. Acknowledge bit Start bit Read/Write bit Slave Address Address Byte R/W ACK When the customer first receives any new MCP4728 device, its default address bit setting is "000". The customer can reprogram the I2C address bits into the EEPROM by using "Write Address Bit" command. This write command needs current address bits. If the address bits are unknown, the user can find them by sending "General Call Read Address" Command. The LDAC pin is also used to select the device of interest to be programmed or to read the current address. The following steps are needed for the I2C address programming. (a) Read the address bits using "General Call Read Address" Command. (This is the case when the address is unknown.) (b) Write I2C address bits using "Write I2C Address Bits" Command. The write address command will replace the current address with a new address in both input registers and EEPROM. See Section 5.4.4 "General call Read Address Bits" for the details of reading the address bits, and Section 5.6.8 "Write Command: Write I2C Address bits (C2=0, C1=1, C0=1)" for writing the address bits. Slave Address for MCP4728 Device Code Address Bits 1 1 0 0 A2 A1 A0 Note: Device Code: Programmed (hard-wired) at the factory. Address Bits: Reprogrammable into EEPROM by the user. FIGURE 5-2: Device Addressing. DS22187A-page 30 (c) 2009 Microchip Technology Inc. MCP4728 www..com 5.4 I2C General Call Commands 5.4.1 GENERAL CALL RESET The device acknowledges the general call address command (0x00 in the first byte). The meaning of the general call address is always specified in the second byte. The I2C specification does not allow to use "00000000" (00h) in the second byte. Please refer to the Philips I2C document for more details of the General Call specifications. The MCP4728 device supports the following I2C General Calls: * * * * General Call Reset General Call Wake-Up General Call Software Update General Call Read Address Bits The General Call Reset occurs if the second byte is "00000110" (06h). At the acknowledgement of this byte, the device will abort the current conversion and perform the following tasks: * Internal reset similar to a Power-On-Reset (POR). The contents of the EEPROM are loaded into each DAC input and output registers immediately. * VOUT will be available immediately regardless of the LDAC pin condition. Start 1 Clock Pulse (CLK Line) 2 3 4 5 6 7 8 9 1 2 3 ACK (MCP4728) Stop 4 5 6 7 8 9 1st Byte (General Call Command) Data (SDA Line) 2nd Byte (Command Type = General Call Reset) Note 1 Note 1: At this falling edge of the last ACK clock bit: a. Startup Timer starts a reset sequence and b. EEPROM data is loaded into the DAC Input and Output Registers immediately. FIGURE 5-3: 5.4.2 General Call Reset. GENERAL CALL WAKE-UP If the second byte is "00001001" (09h), the device will reset the Power-Down bits (PD1,PD0 = 0,0). ACK (MCP4728) Clock Pulse (CLK Line) Start 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 Stop 1st Byte (General Call Command) Data (SDA Line) 2nd Byte (Command Type = General Call Wake-Up) Note 1 Note 1: Resets Power-Down bits at this falling edge of the last ACK clock bit. FIGURE 5-4: General Call Wake-Up. (c) 2009 Microchip Technology Inc. DS22187A-page 31 MCP4728 www..com 5.4.3 GENERAL CALL SOFTWARE UPDATE If the second byte is "00001000" (08h), the device updates all DAC analog outputs (VOUT) at the same time. ACK (MCP4728) Start 1 Clock Pulse (CLK Line) 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 Stop 1st Byte (General Call Command) Data (SDA Line) 2nd Byte (Command Type = General Call Software Update) Note 1 Note 1: At this falling edge of the last ACK clock bit, VOUT A, VOUT B, VOUT C, VOUT D are updated. FIGURE 5-5: General Call Software Update. DS22187A-page 32 (c) 2009 Microchip Technology Inc. MCP4728 www..com 5.4.4 GENERAL CALL READ ADDRESS BITS This command is used to read the I2C address bits of the device. If the second byte is "00001100" (0Ch), the device will output its address bits stored in EEPROM and register. This command uses the LDAC pin to select the device of interest to read on the I2C bus. The LDAC pin needs a logic transition from "High" to "Low" during the negative pulse of the 8th clock of the second byte, and stays "Low" until the end of the 3rd byte. The maximum clock rate for this command is 400 kHz. ACK (MCP4728) Start Restart Pulse 4th Byte ACK (Master) Stop S 0 0 0 0 0 0 0 0 A 0 0 0 0 1 1 0 0 A S 1 1 0 0 X X X 1 A A2 A1 A0 1 A2 A1 A0 0 A P 1st Byte (General Call Address) 2nd Byte 3rd Byte Restart Byte Address Bits Address Bits in in Input EEPROM Register Reading Address Bits LDAC Pin (Notes 1, 2, 3) Note 3 Clock and LDAC Transition Details: ACK Clock Clock Pulse (CLK Line) 6 2nd Byte 7 8 9 S Restart Clock ACK Clock 1 2 3 4 5 6 7 8 9 1 2 3 3rd Byte 4th Byte Reading Address Bits LDAC Pin Note 2 (a) Note 2(b, c) Note 2(b) Note 3 Stay "Low" until the end of the 3rd Byte Note 1: Clock Pulse and LDAC Transition Details. 2: LDAC pin events at the 2nd and 3rd bytes. a. b. Keep LDAC pin "High" until the end of the positive pulse of the 8th clock of the 2nd byte. LDAC pin makes a transition from "High" to "Low" during the negative pulse of the 8th clock of the 2nd byte (just before the rising edge of the 9th clock) and stays "Low" until the rising edge of clock 9 of the 3rd byte. The MCP4728 device does not acknowledge the 3rd byte if the conditions (a) and (b) are not met. c. 3: LDAC pin resumes its normal function after "Stop" bit. FIGURE 5-6: General Call Read I2C Address. (c) 2009 Microchip Technology Inc. DS22187A-page 33 MCP4728 www..com 5.5 Writing and Reading Registers and EEPROM 5.6 Write Commands for DAC Registers and EEPROM The Master (MCU) can write or read the DAC input registers or EEPROM using the I2C interface command. The following sections describe the communication examples to write and read the DAC registers and EEPROM using the I2C interface. Table 5-1 summarizes the write command types and their functions.The write command is defined by using three write command type bits (C2, C1, C0) and two write function bits (W1, W0). The register selection bits (DAC1, DAC0) are used to select the DAC channel. TABLE 5-1: Command Field C2 C1 C0 WRITE COMMAND TYPES Write Function W1 W0 Command Name Function Fast Mode Write 0 0 X Not Used Fast Write for DAC Input Registers This command writes to the DAC input registers sequentially with limited configuration bits. The data is sent sequentially from channels A to D. The input register is written at the acknowledge clock pulse of the channel's last input data byte. EEPROM is not affected. (Note 1) This command writes to multiple DAC input registers, one DAC input register at a time. The writing channel register is defined by the DAC selection bits (DAC1, DAC0). EEPROM is not affected. (Note 2) This command writes to both the DAC input registers and EEPROM sequentially. The sequential writing is carried out from a starting channel to channel D. The starting channel is defined by the DAC selection bits (DAC1 and DAC0). The input register is written at the acknowledge clock pulse of the last input data byte of each register. However, the EEPROM data is written altogether at the same time sequentially at the end of the last byte. (Note 2),(Note 3) This command writes to a single selected DAC input register and its EEPROM. Both the input register and EEPROM are written at the acknowledge clock pulse of the last input data byte. The writing channel is defined by the DAC selection bits (DAC1 and DAC0). (Note 2),(Note 3) Write DAC Input Register and EEPROM 0 1 0 0 0 Multi-Write for DAC Input Registers Sequential Write for DAC Input Registers and EEPROM 1 0 1 1 Single Write for DAC Input Register and EEPROM Write I2C Address Bits (A2, A1, A0) 0 1 1 Not Used Write I2C Address Bits This command writes new I2C address bits (A2, A1, A0) to the DAC input register and EEPROM. Write Reference (VREF) selection bits to Input Registers This command writes Reference (VREF) selection bits of each channel. Write VREF, Gain, and Power-Down Select Bits (Note 4) 1 0 0 Not Used 1 1 Note 1: 2: 3: 4: 1 0 0 1 Not Used Not Used Write Gain selection This command writes Gain selection bits of each channel. bits to Input Registers Write Power-Down This command writes Power-Down bits of each channel. bits to Input Registers The analog output is updated when LDAC pin is (or changes to) "Low". UDAC bit is not used for this command. The DAC output is updated when LDAC pin or UDAC bit is "Low". The device starts writing to the EEPROM on the acknowledge clock pulse of the last channel. The device does not execute any command until RDY/BSY bit comes back to "High". The input and output registers are updated at the acknowledge clock pulse of the last byte. The update does not require LDAC pin or UDAC bit conditions. EEPROM is not affected. DS22187A-page 34 (c) 2009 Microchip Technology Inc. MCP4728 www..com 5.6.1 FAST WRITE COMMAND (C2=0, C1=0, C0=X, X = DON'T CARE) 5.6.2 MULTI-WRITE COMMAND: WRITE DAC INPUT REGISTERS (C2=0, C1=1, C0=0; W1=0, W0=0) The Fast Write command is used to update the input DAC registers from channels A to D sequentially. The EEPROM data is not affected by this command. This command is called "Fast Write" because it updates the input registers with only limited data bits. Only the Power-Down mode selection bits (PD1 and PD0) and 12 bits of DAC input data are writable. The input register is updated at the acknowledge pulse of each channel's last data byte. Figure 5-7 shows an example of the Fast Write command. Updating Analog Outputs: a. When the LDAC pin is "High" before the last byte of the channel D, all analog outputs are updated simultaneously by bringing down the LDAC pin to "Low" any time. If the command starts with the LDAC pin "Low", the channel's analog output is updated at the falling edge of the acknowledge clock pulse of the channel's last byte. Send the General Call Software Update command: This command updates all channels simultaneously. Note 1: UDAC bit is not used in this command. This command is used to write DAC input register, one at a time. The EEPROM data is not affected by this command. The DAC selection bits (DAC1, DAC0) select the DAC channel to write. Only a selected channel is affected. Repeated bytes are used to write more multiple DAC registers. The D11 - D0 bits in the third and fourth bytes are the DAC input data of the selected DAC channel. Bytes 2 4 can be repeated for the other channels. Figure 5-8 shows an example of the Multi-Write command. Updating Analog Outputs: The analog outputs can be updated by one of the following events after the falling edge of the acknowledge clock pulse of the 4th byte. a. b. c. When the LDAC pin or UDAC bit is "Low". If UDAC bit is "High", bringing down the LDAC pin to "Low" any time. By sending the General Call Software Update command. Note 1: The UDAC bit can be used effectively to upload the input register to the output register, but it affects only a selected channel only, while the LDAC pin and General Call Software Update command affect all channels. b. c. (c) 2009 Microchip Technology Inc. DS22187A-page 35 MCP4728 www..com 5.6.3 SEQUENTIAL WRITE COMMAND: WRITE DAC INPUT REGISTERS AND EEPROM SEQUENTIALLY FROM STARTING CHANNEL TO CHANNEL D (C2=0, C1=1, C0=0; W1=1, W0=0) 5.6.4 SINGLE WRITE COMMAND: WRITE A SINGLE DAC INPUT REGISTER AND EEPROM (C2=0, C1=1, C0=0; W1=1, W0=1) When the device receives this command, it writes the input data to the DAC input registers sequentially from the starting channel to channel D, and also writes to EEPROM sequentially. The starting channel is determined by the DAC1 and DAC0 bits. Table 5-2 shows the functions of the channel selection bits for the sequential write command. When the device is writing EEPROM, the RDY/BSY bit stays "Low" until the EEPROM write operation is completed. The state of the RDY/BSY bit flag can be monitored by a read command or at the RDY/BSY pin. Any new command received during the EEPROM write operation (RDY/BSY bit is "Low") is ignored. Figure 5-9 shows an example of the sequential write command. When the device receives this command, it writes the input data to a selected single DAC input register and also to its EEPROM. The channel is selected by the channel selection bits (DAC1 and DAC0). See Table 4-3 for the channel selection bit function. Figure 5-10 shows an example of the single write command. Updating Analog Outputs: The analog outputs can be updated by one of the following events after the falling edge of the acknowledge clock pulse of the 4th byte. a. b. c. When the LDAC pin or UDAC bit is "Low". If UDAC bit is "High", bringing down the LDAC pin to "Low" any time. By sending the General Call Software Update command. Note 1: The UDAC bit can be used effectively to upload the input register to the output register, but it affects only a selected channel only, while the LDAC pin and General Call Software Update command affect all channels. Updating Analog Outputs: The analog outputs can be updated by one of the following events after the falling edge of the acknowledge clock pulse of the 4th byte. a. b. c. When the LDAC pin or UDAC bit is "Low". If UDAC bit is "High", bringing down the LDAC pin to "Low" any time. By sending the General Call Software Update command. Note 1: The UDAC bit can be used effectively to upload the input register to the output register, but it affects only a selected channel only, while the LDAC pin and General Call Software Update command affect all channels. TABLE 5-2: DAC CHANNEL SELECTION BITS FOR SEQUENTIAL WRITE COMMAND Channels Ch. A - Ch. D Ch. B - Ch. D Ch. C - Ch. D Ch. D 0 1 0 1 DAC1 0 0 1 1 DAC0 DS22187A-page 36 (c) 2009 Microchip Technology Inc. MCP4728 www..com 5.6.5 WRITE COMMAND: SELECT VREF BIT (C2=1, C1=0, C0=0) 5.6.8 WRITE COMMAND: WRITE I2C ADDRESS BITS (C2=0, C1=1, C0=1) When the device receives this command, it updates the DAC voltage reference selection bit (VREF) of each channel. The EEPROM data is not affected by this command. The affected channel's analog output is updated after the acknowledge pulse of the last byte. Figure 5-12 shows an example of the write command for Select VREF bits. This command writes new I2C address bits (A2, A1, A0) to the DAC input registers and EEPROM. When the device receives this command, it overwrites the current address bits with the new address bits. This command is valid only when the LDAC pin makes a transition from "High" to "Low" at the low time of the last bit (8th clock) of the second byte, and stays "Low" until the end of the 3rd byte. The update occurs after "Stop" bit if the conditions are met. The LDAC pin is used to select a device of interest to write. The highest clock rate of this command is 400 kHz. Figure 5-11 shows the details of the address write command. Note 1: To write a new device address, it needs the current address of the device. The current address bits can be read out by sending General Call Read Address Bits command. See 5.4.4 "General call Read Address Bits" for more details of reading the I2C address bits. 5.6.6 WRITE COMMAND: SELECT POWER-DOWN BITS (C2=1, C1=0, C0=1) When the device receives this command, it updates the Power-Down selection bits (PD1, PD0) of each channel. The EEPROM data is not affected by this command. The affected channel is updated after the acknowledge pulse of the last byte. Figure 5-13 shows an example of the write command for the Select Power-Down bits. 5.6.7 WRITE COMMAND: SELECT GAIN BIT (C2=1, C1=1, C0=0) When the device receives this command, it updates the gain selection bits (GX) of each channel. The EEPROM data is not affected by this command. The analog output is updated after the acknowledge pulse of the last byte. Figure 5-14 shows an example of the write command for select gain bits. 5.6.9 READ COMMAND If the R/W bit is set to a logic "High" in the I2C serial communications command, the device enters a reading mode and reads out the input registers and EEPROM. Figure 5-15 shows the details of the read command. Note 1: The device address bits are read by using General Call Read Address Bits command. (c) 2009 Microchip Technology Inc. DS22187A-page 37 MCP4728 www..com Command Type Bits: C2=0 C1=0 C0=X ACK (MCP4728) Start S 1 1 0 1st byte 0 A2 A1 A0 R/W 0 A (C2 C1) 0 2nd Byte 3rd Byte 0 PD1 PD0 D11 D10 D9 D8 A D7 D6 D5 D4 D3 D2 D1 D0 A Device Addressing Fast Write Command DAC Input Register of Channel A Update Channel A DAC Input Register at this ACK pulse. ACK (MCP4728) 2nd Byte X 3rd Byte X PD1 PD0 D11 D10 D9 D8 A D7 D6 D5 D4 D3 D2 D1 D0 A DAC Input Register of Channel B Update Channel C DAC Input Register at this ACK pulse. ACK (MCP4728) 2nd Byte X 3rd Byte X PD1 PD0 D11 D10 D9 D8 A D7 D6 D5 D4 D3 D2 D1 D0 A DAC Input Register of Channel C Update Channel C DAC Input Register at this ACK pulse. ACK (MCP4728) 2nd Byte X 3rd Byte X PD1 PD0 D11 D10 D9 D8 A D7 D6 D5 D4 D3 D2 D1 D0 A DAC Input Register of Channel D Update Channel C DAC Input Register at this ACK pulse. Repeat Bytes P Stop Note 1: X is don't care bit. VOUT can be updated after the last byte's ACK pulse is issued and by bringing down the LDAC pin to "Low". FIGURE 5-7: Fast Write Command: Write DAC Input Registers Sequentially from Channel A to D. DS22187A-page 38 (c) 2009 Microchip Technology Inc. MCP4728 www..com Command Type Bits: C2=0 C1=1 C0=0 W1=0 W0=0 ACK (MCP4728) Start S 1 1 0 1st byte 0 A2 A1 A0 0 R/W Device Addressing A ACK (MCP4728) (C2 C1 C0 W1 W2) 0 1 0 0 2nd Byte 3rd Byte 4th Byte 0 DAC1 DAC0 UDAC A VREF PD1 PD0 Gx D11 D10 D9 D8 A D7 D6 D5 D4 D3 D2 D1 D0 A Multi-Write Command Channel Select DAC Input Register of Selected Channel Note 1 Repeat Bytes of the 2nd - 4th Bytes ACK (MCP4728) 2nd byte XXX X 3rd Byte 4th Byte X DAC1 DAC0 UDAC A VREF PD1 PD0 Gx D11 D10 D9 D8 A D7 D6 D5 D4 D3 D2 D1 D0 A Note 3 Note 2 DAC Input Register of Selected Channel Note 1 Repeat Bytes of the 2nd - 4th Bytes P Stop Note 1: 2: VOUT Update: If UDAC = 0 or LDAC Pin = 0: VOUT is updated after the 4th byte's ACK is issued. The user can write to the other channels by sending repeated bytes with new channel selection bits (DAC1, DAC0). 3: X is don't care bit. FIGURE 5-8: Multi-Write Command: Write DAC Input Registers. (c) 2009 Microchip Technology Inc. DS22187A-page 39 MCP4728 www..com Command Type Bits: C2=0 C1=1 C0=0 W1=1 W0=0 ACK (MCP4728) Start S 1 1 0 1st byte 0 A2 A1 A0 0 R/W Device Addressing A ACK (MCP4728) (C2 C1 C0 W1 W2) 0 1 0 1 2nd Byte 3rd Byte 4th Byte 0 DAC1 DAC0 UDAC A VREF PD1 PD0 Gx D11 D10 D9 D8 A D7 D6 D5 D4 D3 D2 D1 D0 A Sequential Write Sequential Write Channel Select Command DAC Input Register of Selected Channel Note 1 Repeat Bytes of the 3rd - 4th Bytes ACK (MCP4728) 3rd Byte 4th Byte P Stop VREF PD1 PD0 Gx D11 D10 D9 D8 A D7 D6 D5 D4 D3 D2 D1 D0 A DAC Input Register of Channel D Notes 1 and 2 Note 1: 2: VOUT Update: If UDAC = 0 or LDAC Pin = 0: VOUT is updated after the 4th byte's ACK is issued. EEPROM Write: The MCP4728 device starts writing EEPROM at the falling edge of the 4th byte's ACK pulse. FIGURE 5-9: Sequential Write Command: Write DAC Input Registers and EEPROM Sequentially from Starting Channel to Channel D. Note that this command can send up to 10 bytes including the device addressing and command bytes. Any byte after the 10th byte is ignored. DS22187A-page 40 (c) 2009 Microchip Technology Inc. MCP4728 www..com Command Type Bits: C2=0 C1=1 C0=0 W1=1 W0=1 ACK (MCP4728) Start S 1 1 0 1st byte 0 A2 A1 A0 0 R/W Device Addressing A ACK (MCP4728) C2 C1 C0 W1 W0 0 1 0 1 2nd Byte 3rd Byte 4th Byte Stop 1 DAC1 DAC0 UDAC A VREF PD1 PD0 Gx D11 D10 D9 D8 A D7 D6 D5 D4 D3 D2 D1 D0 A P Single Write Command Channel Select DAC Input Register of Selected Channel Note 1 and Note 2 Note 1: 2: VOUT Update: If UDAC = 0 or LDAC Pin = 0: VOUT is updated after the 4th byte's ACK is issued. EEPROM Write: The MCP4728 device starts writing EEPROM at the falling edge of the 4th byte's ACK pulse. FIGURE 5-10: Single Write Command: Write to a Single DAC Input Register and EEPROM. (c) 2009 Microchip Technology Inc. DS22187A-page 41 MCP4728 www..com Command Type Bits: C2=0 C1=1 C0=1 Start 1st Byte (C2 C1 C0) 2nd Byte 3rd Byte 1 4th Byte Stop S 1 1 0 0 A2 A1 A0 0 A 0 1 1 A2 A1 A0 0 1 A 0 1 1 A2 A1 A0 1 0 A 0 Current R/W Command Current Device Type Address Bits Code Address Bits Command Current Type Address Bits 1 A2 A1 A0 1 1 A P Command New Address Bits (for confirmation) Type Note 4 LDAC Pin (Notes 1, 2, 3) Note 3 Clock and LDAC Transition Details: ACK (MCP4728) Clock Pulse (CLK Line) 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 ----9 Stop P 2nd Byte 3rd Byte 4th Byte Note 4 LDAC Pin Note 2 (a) Note 2(b) Note 2(b) Note 3 Stay "Low" during this 3rd byte Note 1: 2: Clock Pulse and LDAC Transition Details. LDAC pin events at the 2nd and 3rd bytes. a. b. Keep LDAC pin "High" until the end of the positive pulse of the 8th clock of the 2nd byte. LDAC pin makes a transition from "High" to "Low" during the negative pulse of the 8th clock of the 2nd byte (just before the rising edge of the 9th clock), and stays "Low" until the rising edge of the 9th clock of the 3rd byte. The MCP4728 device does not acknowledge the 3rd byte if the conditions (a) and (b) are not met. c. 3: 4: LDAC pin resumes its normal function after "Stop" bit. EEPROM Write/ a. b. Charge Pump initiates the EEPROM write sequence at the falling edge of the 4th byte's ACK pulse. The RDY/BSY bit (pin) goes "Low" at the falling edge of this ACK clock and back to "High" immediately after the EEPROM write is completed. FIGURE 5-11: Write Command: Write I2C Address Bits to the DAC Registers and EEPROM. DS22187A-page 42 (c) 2009 Microchip Technology Inc. MCP4728 www..com Command Type Bits: C2=1 C1=0 C0=0 ACK (MCP4728) Start S 1 1 0 1st byte 0 A2 A1 A0 0 R/W Device Addressing A (C2 C1 C0) 1 0 0 X 2nd Byte VREF A VREF B VREF C VREF D A Stop P Write Command Note 1 Registers and VOUT are updated at this falling edge of ACK pulse. Note 1: VREF = 0: VDD = 1: Internal Reference (2.048V) VREF A = Voltage reference of Channel A VREF B = Voltage reference of Channel B VREF C = Voltage reference of Channel C VREF D = Voltage reference of Channel D 2: X is don't care bit. FIGURE 5-12: Registers. Write Command: Write Voltage Reference Selection Bit (VREF) to the DAC Input Command Type Bits: C2=1 C1=0 C0=1 ACK (MCP4728) Start S 1 1 0 1st byte 0 A2 A1 A0 0 R/W Device Addressing A ACK (MCP4728) (C2 C1 C0) 1 0 1 X 2nd Byte PD1 A PD0 A PD1 B PD0 B A PD1 C PD0 C PD1 D 3rd Byte PD0 D X X X X Stop A P Write Command Channel A Channel B Channel C Channel D Registers and VOUT are updated at this falling edge of ACK pulse. Note 1: X is don't care bit. FIGURE 5-13: Registers. Write Command: Write Power-Down Selection Bits (PD1, PD0) to the DAC Input (c) 2009 Microchip Technology Inc. DS22187A-page 43 MCP4728 www..com Command Type Bits: C2=1 C1=1 C0=0 ACK (MCP4728) Start S 1 1 0 1st Byte 0 A2 A1 A0 0 R/W A (C2 C1 C0) 1 1 0 2nd Byte GX A GX B GX C GX D A Note 1 Stop P Device Addressing Write Command Registers and VOUT are updated at this falling edge of ACK pulse. Note 1: GXA = Gain Selection for Channel A GXB = Gain Selection for Channel B GXC = Gain Selection for Channel C GXD = Gain Selection for Channel D Ex: GXA = 0: Gain of 1 for Channel A = 1: Gain of 2 for Channel A 2: X is don't care bit. FIGURE 5-14: Write Command: Write Gain Selection Bit (GX) to the DAC Input Registers. DS22187A-page 44 (c) 2009 Microchip Technology Inc. MCP4728 www..com ACK (MCP4728) Read Command Start S 1 1 0 0 A2 A1 A0 1 R/W Device Code Address Bits ACK (MCP4728) 2nd Byte RDY/ BSY POR DAC1 DAC 0 0 A2 A1 A0 A VREF A 3rd Byte 4th Byte Stop PD1 PD0 GX D11 D10 D9 D8 A D7 D6 D5 D4 D3 D2 D1 D0 A P Channel A DAC Input Register 5th Byte RDY/ BSY POR DAC1 DAC 0 0 A2 A1 A0 A VREF 6th Byte 7th Byte Stop PD1 PD0 GX D11 D10 D9 D8 A D7 D6 D5 D4 D3 D2 D1 D0 A P Channel A DAC EEPROM 2nd Byte RDY/ BSY POR DAC1 DAC 0 0 A2 A1 A0 A VREF 3rd Byte 4th Byte Stop PD1 PD0 GX D11 D10 D9 D8 A D7 D6 D5 D4 D3 D2 D1 D0 A P Channel B DAC Input Register 5th Byte RDY/ BSY POR DAC1 DAC 0 0 A2 A1 A0 A VREF 6th Byte 7th Byte Stop PD1 PD0 GX D11 D10 D9 D8 A D7 D6 D5 D4 D3 D2 D1 D0 A P Channel B DAC EEPROM 2nd Byte RDY/ BSY POR DAC1 DAC 0 0 A2 A1 A0 A VREF 3rd Byte 4th Byte Stop PD1 PD0 GX D11 D10 D9 D8 A D7 D6 D5 D4 D3 D2 D1 D0 A P Channel C DAC Input Register 5th Byte RDY/ BSY POR DAC1 DAC 0 0 A2 A1 A0 A VREF 6th Byte 7th Byte Stop PD1 PD0 GX D11 D10 D9 D8 A D7 D6 D5 D4 D3 D2 D1 D0 A P Channel C DAC EEPROM 2nd Byte RDY/ BSY POR DAC1 DAC 0 0 A2 A1 A0 A VREF 3rd Byte 4th Byte Stop PD1 PD0 GX D11 D10 D9 D8 A D7 D6 D5 D4 D3 D2 D1 D0 A P Channel D DAC Input Register 5th Byte RDY/ BSY POR DAC1 DAC 0 0 A2 A1 A0 A VREF 6th Byte 7th Byte Stop PD1 PD0 GX D11 D10 D9 D8 A D7 D6 D5 D4 D3 D2 D1 D0 A P Channel D DAC EEPROM Note 1: Repeat The 2nd - 4th bytes are the contents of the DAC Input Register and the 5th - 7th bytes are the EEPROM contents. The device outputs sequentially from channel A to D. POR Bit: 1 = Set (Device is powered on with VDD > VPOR), 0 = Powered off state. FIGURE 5-15: Read Command and Device Outputs. DS22187A-page 45 (c) 2009 Microchip Technology Inc. MCP4728 www..com NOTES: DS22187A-page 46 (c) 2009 Microchip Technology Inc. MCP4728 www..com 6.0 6.1 TERMINOLOGY Resolution 7 INL = < -1 LSB 6 5 Analog 4 Output (LSB) 3 2 1 0 000 001 010 011 100 101 110 111 DAC Input Code INL = - 1 LSB The resolution is the number of DAC output states that divide the full scale range. For the 12-bit DAC, the resolution is 212, meaning the DAC code ranges from 0 to 4095. 6.2 LSB INL = 0.5 LSB The least significant bit or the ideal voltage difference between two successive codes. EQUATION 6-1: V REF LSB = -----------n 2 ( V Full Scale - V Zero Scale ) = --------------------------------------------------------12 2 -1 ( V Full Scale - V Zero Scale ) = --------------------------------------------------------4095 = = n = If external reference is selected 2.048V If internal reference is selected The number of digital input bits, n = 12 for MCP4728. VDD Ideal Transfer Function Actual Transfer Function FIGURE 6-1: INL Accuracy. Where VREF 6.4 Differential Nonlinearity (DNL) Differential nonlinearity (DNL) error (see Figure 6-2) is the measure of step size between codes in actual transfer function. The ideal step size between codes is 1 LSB. A DNL error of zero would imply that every code is exactly 1 LSB wide. If the DNL error is less than 1 LSB, the DAC guarantees monotonic output and no missing codes. The DNL error between any two adjacent codes is calculated as follows: 6.3 Integral Nonlinearity (INL) Integral nonlinearity (INL) error is the maximum deviation of an actual transfer function from an ideal transfer function (straight line). In the MCP4728, INL is calculated using two end-points (zero and full scale). INL can be expressed as a percentage of full scale range (FSR) or in fraction of an LSB. INL is also called relative accuracy. Equation 6-2 shows how to calculate the INL error in LSB and Figure 6-1 shows an example of INL accuracy. EQUATION 6-3: DNL Where: DNL ERROR V OUT - LSB = --------------------------------LSB DNL is expressed in LSB. VOUT = The measured DAC output voltage difference between two adjacent input codes. EQUATION 6-2: INL ERROR ( V OUT - V Ideal ) INL = -------------------------------------LSB Where: INL is expressed in LSB = Code*LSB VIdeal VOUT = The output voltage measured at the given input code (c) 2009 Microchip Technology Inc. DS22187A-page 47 MCP4728 www..com 7 6 5 DNL = 2 LSB Analog 4 Output (LSB) 3 2 1 0 000 001 010 011 100 101 110 111 DAC Input Code DNL = 0.5 LSB For the MCP4728 device, the gain error is not calibrated at the factory and most of the gain error is contributed by the output buffer (op amp) saturation near the code range beyond 4000. For applications that need the gain error specification less than 1% maximum, a user may consider using the DAC code range between 100 and 4000 instead of using full code range (code 0 to 4095). The DAC output of the code range between 100 and 4000 is much more linear than full scale range (0 to 4095). The gain error can be calibrated out by software in applications. 6.7 Full Scale Error (FSE) Full scale error (see Figure 6-4) is the sum of offset error plus gain error. It is the difference between the ideal and measured DAC output voltage with all bits set to one (DAC input code = FFFh). Ideal Transfer Function Actual Transfer Function EQUATION 6-4: ( V OUT - V Ideal ) FSE = -------------------------------------LSB Where: FSE is expressed in LSB. VIdeal = (VREF) (1 - 2-n) - Offset Voltage (VOS) VREF = Voltage Reference FIGURE 6-2: DNL Accuracy. 6.5 Offset Error Offset error (see Figure 6-3) is the deviation from zero voltage output when the digital input code is zero (zero scale voltage). This error affects all codes by the same amount. For the MCP4728 device, the offset error is not trimmed at the factory. However, it can be calibrated by software in application circuits. Actual Transfer Function Analog Output Analog Output Ideal Transfer Function Actual Transfer Function Full Scale Error Gain Error Offset Error 0 Actual Transfer Function after Offset Error is removed Ideal Transfer Function DAC Input Code FIGURE 6-3: Offset Error. 0 DAC Input Code 6.6 Gain Error Gain error (see Figure 6-4) is the difference between the actual full scale output voltage from the ideal output voltage of the DAC transfer curve. The gain error is calculated after nullifying the offset error, or full scale error minus the offset error. The gain error indicates how well the slope of the actual transfer function matches the slope of the ideal transfer function. The gain error is usually expressed as percent of full scale range (% of FSR) or in LSB. FIGURE 6-4: Error. Gain Error and Full Scale 6.8 Gain Error Drift Gain error drift is the variation in gain error due to a change in ambient temperature. The gain error drift is typically expressed in ppm/C. DS22187A-page 48 (c) 2009 Microchip Technology Inc. MCP4728 www..com 6.9 Offset Error Drift 6.13 Analog Crosstalk Offset error drift is the variation in offset error due to a change in ambient temperature. The offset error drift is typically expressed in ppm/oC. 6.10 Settling Time The Settling time is the time delay required for the DAC output to settle to its new output value from the start of code transition, within specified accuracy. In the MCP4728 device, the settling time is a measure of the time delay until the DAC output reaches its final value within 0.5 LSB when the DAC code changes from 400h to C00h. Analog crosstalk is the glitch that appears at the output of one DAC due to a change in the output of the other DAC. The area of the glitch is expressed in nV-Sec, and measured by loading one of the input registers with a full scale code change (all 0s to all 1s and vice versa) while keeping both UDAC bit and LDAC pin high. Then bring down the LDAC pin to low and measure the output of the DAC whose digital code was not changed. 6.14 DAC-to-DAC Crosstalk 6.11 Major-Code Transition Glitch Major-code transition glitch is the impulse energy injected into the DAC analog output when the code in the DAC register changes state. It is normally specified as the area of the glitch in nV-Sec. and is measured when the digital code is changed by 1 LSB at the major carry transition (Example: 011...111 to 100... 000, or 100... 000 to 011... 111). DAC-to-DAC crosstalk is the glitch that appears at the output of one DAC due to an input code change and subsequent output change of the other DAC. This includes both digital and analog crosstalks. The area of the glitch is expressed in nV-Sec, and measured by loading one of the input registers with a full scale code change (all 0s to all 1s and vice versa) while keeping UDAC bit or LDAC pin low. 6.15 Power-Supply Rejection Ratio (PSRR) 6.12 Digital Feedthrough Digital feedthrough is the glitch that appears at the analog output caused by coupling from the digital input pins of the device. The area of the glitch is expressed in nV-Sec, and is measured with a full scale change (Example: all 0s to all 1s and vice versa) on the digital input pins. The digital feedthrough is measured when the DAC is not being written to the output register. This condition can be created by writing input register with both UDAC bit and LDAC pin high. PSRR indicates how the output of the DAC is affected by changes in the supply voltage. PSRR is the ratio of the change in VOUT to a change in VDD for full scale output of the DAC. It is measured on one DAC that is using an internal VREF while the VDD is varied +/- 10%, and expressed in dB or V/V. (c) 2009 Microchip Technology Inc. DS22187A-page 49 MCP4728 www..com NOTES: DS22187A-page 50 (c) 2009 Microchip Technology Inc. MCP4728 www..com 7.0 TYPICAL APPLICATIONS 7.1 The MCP4728 device is a part of Microchip's latest DAC family with non-volatile EEPROM memory. The device is a general purpose resistor string DAC intended to be used in applications where a precision, and low power DAC with moderate bandwidth is required. Since the device includes non-volatile EEPROM memory, the user can use this device for applications that require the output to return to the previous set-up value on subsequent power-ups. Applications generally suited for the MCP4728 device family include: * * * * Set Point or Offset Trimming Sensor Calibration Portable Instrumentation (Battery Powered) Motor Speed Control Connecting to I2C BUS using Pull-Up Resistors The SCL, SDA, and RDY/BSY pins of the MCP4728 device are open-drain configurations. These pins require a pull-up resistor as shown in Figure 7-1. The LDAC pin has a schmitt trigger input configuration and it can be driven by an external MCU I/O pin. The pull-up resistor values (R1 and R2) for SCL and SDA pins depend on the operating speed (standard, fast, and high speed) and loading capacitance of the I2C bus line. Higher value of pull-up resistor consumes less power, but increases the signal transition time (higher RC time constant) on the bus line. Therefore, it can limit the bus operating speed. A lower resistor value, on the other hand, consumes higher power, but allows for higher operating speed. If the bus line has higher capacitance due to long metal traces or multiple device connections to the bus line, a smaller pull-up resistor is needed to compensate the long RC time constant. The pull-up resistor is typically chosen between 1 k and 10 k ranges for standard and fast modes, and less than 1 k for high speed mode. VDD C1 R1 R2 R3 VDD 1 SCL 2 SDA 3 LDAC 4 RDY/BSY 5 MCP4728 10 VSS C2 9 VOUT D 8 VOUT C 7 VOUT B 6 VOUT A Analog Outputs To MCU R1 - R3 are the pull-up resistors: R1 and R2: 5 k - 10 k for fSCL = 100 kHz to 400 kHz ~700 for fSCL = 3.4 MHz R3: ~ 100 k C1: 0.1 F, Ceramic capacitor C2: 10 F, Tantalum capacitor FIGURE 7-1: Example of the MCP4728 Device Connection. (c) 2009 Microchip Technology Inc. DS22187A-page 51 MCP4728 www..com 7.1.1 DEVICE CONNECTION TEST 7.3 Power Supply Considerations The user can test the presence of the MCP4728 device on the I2C bus line without performing a data conversion. This test can be achieved by checking an acknowledge response from the MCP4728 device after sending a read or write command. Figure 7-2 shows an example with a read command: a. b. Set the R/W bit "High" or "Low" in the address byte. Check the ACK pulse after sending the address byte. If the device acknowledges (ACK = 0) the command, then the device is connected, otherwise it is not connected. Send Stop bit. Address Byte c. The power source should be as clean as possible. The power supply to the device is used for both VDD and DAC voltage reference by selecting VREF = VDD. Any noise induced on the VDD line can affect DAC performance. A typical application will require a bypass capacitor in order to filter out high frequency noise on the VDD line. The noise can be induced onto the power supply's traces or as a result of changes on the DAC output. The bypass capacitor helps to minimize the effect of these noise sources on signal integrity. Figure 7-1 shows an example of using two bypass capacitors (a 10 F tantalum capacitor and a 0.1 F ceramic capacitor) in parallel on the VDD line. These capacitors should be placed as close to the VDD pin as possible (within 4 mm). If the application circuit has separate digital and analog power supplies, the VDD and VSS pins of the MCP4728 device should reside on the analog plane. SCL 1 2 3 4 5 6 7 8 9 7.4 Using Power Saving Feature SDA Start Bit 1 1 0 1 A2 A1 A0 1 Device Code Address bits R/W Stop Bit The device consumes very little power when it is in Power-Down (shut-down) mode. During the Power-Down mode, most circuits in the selected channel are turned off. It is recommended to power down any unused channel. The device consumes the least amount of power if it enters the Power-Down mode after the internal voltage reference is disabled. This can be achieved by selecting VDD as the voltage reference for all 4 channels and then issuing the Power-Down mode for all channels. MCP4728 Response FIGURE 7-2: I2C Bus Connection Test. 7.2 Layout Considerations ACK Inductively-coupled AC transients and digital switching noise from other devices can affect DAC performance and DAC output signal integrity. Careful board layout will minimize these effects. Bench testing has shown that a multi-layer board utilizing a low-inductance ground plane, isolated inputs, isolated outputs and proper decoupling are critical to achieving good DAC performance. Separate digital and analog ground planes are recommended. In this case, the VSS pin and the ground pins of the VDD capacitors of the MCP4728 should be terminated to the analog ground plane. 7.5 Using Non-Volatile EEPROM Memory The user can store the I2C device address bits, configuration bits and DAC input code of each channel in the on-board non-volatile EEPROM memory using the I2C write command. The contents of EEPROM are readable and writable using the I2C command. When the MCP4728 device is first powered-up or receives General Call Reset Command, it uploads the EEPROM contents to the DAC output registers automatically and provides analog outputs immediately with the saved settings in EEPROM. This feature is very useful in applications where the MCP4728 device is used to provide set points or calibration data for other devices in the application systems. The MCP4728 device can save important system parameters when the application system experiences power failure. See Section 5.5 "Writing and Reading Registers and EEPROM" for more details of using the non-volatile EEPROM memory. DS22187A-page 52 (c) 2009 Microchip Technology Inc. MCP4728 www..com 7.6 Application Examples 7.6.1 The MCP4728 device is a rail-to-rail output DAC designed to operate with a VDD range of 2.7V to 5.5V. Its output amplifier of each channel is robust enough to drive common, small-signal loads directly, thus eliminating the cost and size of external buffers for most applications. Since each channel has its own configuration bits for selecting the voltage reference, gain, power-down, etc., the MCP4728 device offers great simplicity and flexibility to use for various DAC applications. DC SET POINT OR CALIBRATION VOLTAGE SETTINGS A common application for the MCP4728 device is a digitally-controlled set point or a calibration of variable parameters such as sensor offset or bias point. Figure 7-3 shows an example of the set point settings. Let us consider that the application requires different trip voltages (Trip 1 - Trip 4). Assuming the DAC output voltage requirements are given as shown in Table 7-1, examples of sending the Sequential Write and Fast Write commands are shown in Figure 7-4 and Figure 7-5. TABLE 7-1: DAC Channel VOUT A VOUT B VOUT C VOUT D EXAMPLE: SETTING VOUT OF EACH CHANNEL Voltage Reference VDD VDD Internal Internal DAC Output (VOUT) VDD/2 VDD - 1 LSB 2.048V 4.096V (c) 2009 Microchip Technology Inc. DS22187A-page 53 MCP4728 www..com Light VDD Comparator 1 RSENSE R1 VTRIP1 0.1 R2 Light VDD Comparator 2 RSENSE VDD 0.1 R1 R2 R3 R4 VDD 1 SCL 2 SDA 3 LDAC 4 RDY/BSY 5 MCP4728 10 VSS 10 R1 VTRIP2 R2 0.1 9 VOUT D 8 VOUT C 7 VOUT B 6 VOUT A Analog Outputs RSENSE R1 To MCU R2 VTRIP3 0.1 Comparator 3 Light VDD Light VDD D n = Input Code (0 to 4095) Dn V OUT = V REF x ----------- G x 4096 R2 V TRIP = V OUT ------------------ R 1 + R 2 RSENSE R1 VTRIP4 0.1 Comparator 4 R2 FIGURE 7-3: Using the MCP4728 for Set Point or Threshold Calibration. DS22187A-page 54 (c) 2009 Microchip Technology Inc. MCP4728 www..com ACK (MCP4728) Start R/W UDAC VREF GX S11000000A01010000A00001000A00000000A Dn = 211 = 2048 Update DAC A Input Register at this ACK pulse. 1st Byte Device Addressing Multiple Write Command Selecting Channel A for Starting channel ACK (MCP4728) VREF GX 00001111A11111111A Dn = 4095 Update DAC A Input Register at this ACK pulse. ACK (MCP4728) VREF GX 00001111A11111111A Dn = 2048 Update DAC A Input Register at this ACK pulse. ACK (MCP4728) VREF GX Stop 00001111A11111111AP Dn = 4095 Update DAC A Input Register at this ACK pulse. Expected Output Voltage at Each Channel: Dn V OUT A = V DD x ----------4096 Dn V OUT B = V DD x ----------4096 Dn V OUT C = V REF x ----------4096 Dn V OUT C = V REF x ----------4096 2048 = V DD x ----------4096 4095 = V DD x ----------4096 V DD = ---------2 = (V) (V) ( V DD - LSB ) 2048 G x = 2.048 x ----------- x 2 = 2.048 4096 4095 G x = 2.048 x ----------- x 2 = 4.096 4096 (V) (V) FIGURE 7-4: Sequential Write Command for Setting Test Points in Figure 7-3. (c) 2009 Microchip Technology Inc. DS22187A-page 55 MCP4728 www..com Start 1st Byte 2nd Byte 3rd Byte ....... Stop P S 1 1 0 0 A2 A1 A0 0 A 0 1 1 A2 A1 A0 0 1 A 0 1 1 A2 A1 A0 1 0 A Address Byte Fast Mode Write Command DAC A Next DAC Channels The following example shows the expected analog outputs with the corresponding DAC input codes: DAC A Input Code = 001111-11111111 DAC B Input Code = 000111-11111111 DAC C Input Code = 000011-11111111 DAC D Input Code = 000001-11111111 ( V REF x D n ) V OUT = --------------------------------- G x 4096 (A) Channel A Output: Dn for Channel A = 0FFF (hex) = 4095 (decimal) V OUT A ( V DD x 4095 ) 4096 - 1 1= ----------------------------------- = V DD -------------------- = V DD 1 - ----------- = V DD - LSB 4096 4096 4096 (B) Channel B Output: Dn for Channel B = 07FF (hex) = 2047 (decimal) V OUT B ( V DD x 2047 ) V DD V DD 2048 - 1 2= ----------------------------------- = V DD -------------------- = ------------ 1 - ----------- = ------------ - LSB 4096 4096 2 4096 2 (C) Channel C Output: Dn for Channel C = 03FF (hex) = 1023 (decimal) V DD V DD V DD x 1023 1024 - 1 4V OUT C = ---------------------------------- = V DD -------------------- = ------------ 1 - ----------- = ------------ - LSB 4096 4096 4 4096 4 (D) Channel D Output: Dn for Channel D = 01FF (hex) = 511 (decimal) V DD V DD x 511 V DD 512 - 1 8V OUT D = ------------------------------- = V DD ----------------- = ------------ 1 - ----------- = ------------ - LSB 4096 4096 4096 8 8 FIGURE 7-5: Channels. Example of Writing Fast Write Command for Various VOUT. VREF = VDD for all DS22187A-page 56 (c) 2009 Microchip Technology Inc. MCP4728 www..com 8.0 8.1 DEVELOPMENT SUPPORT Evaluation & Demonstration Boards The MCP4728 Evaluation Board is available from Microchip Technology Inc. This board works with Microchip's PICkitTM Serial Analyzer. The user can easily program the DAC input registers and EEPROM using the PICkit Serial Analyzer, and test out the DAC analog output voltages.The PICkit Serial Analyzer uses the PC Graphic User Interface software. Refer to www.microchip.com for further information on this product's capabilities and availability. FIGURE 8-2: Setup for the MCP4728 Evaluation Board with PICkitTM Serial Analyzer. FIGURE 8-1: Board. MCP4728 Evaluation FIGURE 8-3: Example of PICkitTM Serial User Interface. (c) 2009 Microchip Technology Inc. DS22187A-page 57 MCP4728 www..com NOTES: DS22187A-page 58 (c) 2009 Microchip Technology Inc. MCP4728 www..com 9.0 9.1 PACKAGING INFORMATION Package Marking Information 10-Lead MSOP XXXXXX YWWNNN Example 4728 906256 Legend: XX...X Y YY WW NNN e3 * Note: Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week `01') Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package. In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. (c) 2009 Microchip Technology Inc. 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MCP4728 www..com APPENDIX A: REVISION HISTORY Revision A (June 2009) * Original Release of this Document. (c) 2009 Microchip Technology Inc. DS22187A-page 61 MCP4728 www..com NOTES: DS22187A-page 62 (c) 2009 Microchip Technology Inc. MCP4728 www..com PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. Device X /XX Package Examples: a) MCP4728: Tape and Reel, Extended Temperature, 10LD MSOP package. Temperature Range Device: MCP4728: Single Comparator Temperature Range: E = -40C to +125C Package: UN = Plastic Micro Small Outline Transistor, 10-lead (c) 2009 Microchip Technology Inc. DS22187A-page 63 MCP4728 www..com NOTES: DS22187A-page 64 (c) 2009 Microchip Technology Inc. www..com Note the following details of the code protection feature on Microchip devices: * * Microchip products meet the specification contained in their particular Microchip Data Sheet. Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable." * * * Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, rfPIC and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, nanoWatt XLP, Omniscient Code Generation, PICC, PICC-18, PICkit, PICDEM, PICDEM.net, PICtail, PIC32 logo, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. (c) 2009, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company's quality system processes and procedures are for its PIC(R) MCUs and dsPIC(R) DSCs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001:2000 certified. (c) 2009 Microchip Technology Inc. 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